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AU9368 USB Multi-LUN Flash Card Reader Controller V1.19W
Official Release_ Public
7.7 Latch-Up Test Results
Test Description: Latch-Up testing was performed at room ambient using an
IMCS-4600 system which applies a stepped voltage to one pin per device with all
other pins open except Vdd and Vss which were biased to 5Volts and ground
respectively.
Testing was started at 5.0V (Positive) or 0V (Negative), and the DUT was biased for
0.5 seconds.
If neither the PUT current supply nor the device current supply reached the
predefined limit (DUT=00mA, Icc=100mA), then the voltage was increased by
0.1Volts and the pin was tested again.
The JEDEC JC-40.2 CMOS Logic standardization committee recommended this
procedure.
Notes:
1. DUT: The device under test.
2. PUT: The pin under test.
Figure 7.3 Latch-Up Test Results
Test Circuit: Positive Input/Output Overvoltage/Overcurrent
