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AKM AKD4128A-A, Manual

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AKM AKD4128A-A Manual Download Page 24

   [AKD4128A-A] 

[KM104301]  

2010/09 

- 24 - 

 

■

Dialog Boxes 

 

  [All Req Write] 

 

Click [All Reg Write] button in the main window to open register setting files.   
Register setting files saved by [SAVE] button can be applied.   

 

 

Figure 4. Window of [ All Reg Write] 

 
  [Open (left)]    : Selecting a register setting file (*.akr). 
 [Write] 

   : 

Executing 

register 

writing. 

 

  [Write All]     : Executing all register writings. 

Writings are executed in descending order.   

 [Help]    : 

Help 

window 

is 

popped 

up. 

 

  [Save]        : Saving the register setting file assignment. The file name is “*.mar”.   
  [Open (right)]   : Opening a saved register setting file assignment “*. mar”.   
 [Close] 

   : 

Closing 

the 

dialog 

box 

and 

finish 

the 

process. 

 

   

*Operating Suggestions   

(1) Those files saved by [Save] button and opened by [Open] button on the right of the dialog “*.mar” should be 

stored in the same folder.   

(2) When register settings are changed by [Save] button in the main window, re-read the file to reflect new register 

settings. 

 

Summary of Contents for AKD4128A-A

Page 1: ...rd FUNCTION DIR DIT with optical or coaxial input output 10pin Header for AKM AD DA evaluation board Opt In AK4114 DIR 10pin Header 5V GND Opt Out AK4114 DIT 10pin Header AK4128A COAX Regu lator COAX Opt In AK4114 DIR 10pin Header COAX Opt In AK4114 DIR 10pin Header COAX Opt In AK4114 DIR 10pin Header COAX DVDD AVDD Regu lator Regu lator D3 3V 1 D3 3V 2 10pin Header I2 C Figure 1 AKD4128A A Block ...

Page 2: ...ed 3 3V DVDD of AK4128A Should be always connected when DVDD of AK4128A is not supplied from regulator T1 In this case JP2 is set to DVDD side Open D3 3V 1 Red 3 3V AK4114 Digital Logic Should be always connected when AK4114 and Digital Logic is not supplied from regulator T2 In this case JP3 is set to D3 3V 1 side Open D3 3V 2 Red 3 3V AK4114 Digital Logic Should be always connected when AK4114 a...

Page 3: ...D of AK4128A a When using DVDD jack b When using Regulator DVDD SEL JP2 REG DVDD 3 DVDD SEL JP2 REG DVDD 3 3 Setup the D3 3V 1 AK4114 and Digital Logic a When using D3 3V 1 jack b When using Regulator D3 3V 1 SEL JP3 D3 3V 1 REG 3 D3 3V 1 SEL JP3 D3 3V 1 REG 3 4 Setup the D3 3V 2 AK4114 and Digital Logic a When using D3 3V 2 jack b When using Regulator D3 3V 2 SEL JP4 REG D3 3V 2 3 D3 3V 2 SEL JP4...

Page 4: ...g DIR function of AK4114 U2 U3 U4 and U5 1 2 When using all clocks are fed through the 10pin port 2 Setting for Output port 2 1 When using DIT function of AK4114 U6 2 2 When using all clocks are fed through the 10pin port PORT5 3 Other jumper pins setup 4 Power on The AK4128A should be reset once bringing SW2 PDN L upon power up ...

Page 5: ...othing should be connected to PORT1 4 1 1 1 Setup the RX a Select to Optical jack Default b Select to BNC jack IN PU T x SE L BN C O PT 3 IN PU T x S EL BN C O P T 3 x contains a number 1 4 1 1 2 Setup the IBICK1 4 ILRCK1 4 and SDTI1 4 When using J1 4 COAX and PORT6 9 OPT nothing should be connected to PORT1 4 IBICKx SDTIx ILRCKx IMCLK SEL JP27 EXT DSP1 DIR 2 ６ ５ x contains a number 1 4 ...

Page 6: ...ND SDTI4 SEL JP8 Asynchronous Synchronous GND 2 5 6 2 5 6 2 5 6 2 5 6 b When using Asynchronous Mode INAS pin H SDTI1 SEL JP5 Asynchronous Synchronous GND SDTI2 SEL JP6 Asynchronous Synchronous GND SDTI3 SEL JP7 Asynchronous Synchronous GND SDTI4 SEL JP8 Asynchronous Synchronous GND 2 5 6 2 5 6 2 5 6 2 5 6 c Connect to GND SDTI1 SEL JP5 Asynchronous Synchronous GND SDTI2 SEL JP6 Asynchronous Synch...

Page 7: ... a When using Synchronous Mode INAS pin L Default SDTI1 SEL JP5 Asynchronous Synchronous GND SDTI2 SEL JP6 Asynchronous Synchronous GND SDTI3 SEL JP7 Asynchronous Synchronous GND SDTI4 SEL JP8 Asynchronous Synchronous GND 2 5 6 2 5 6 2 5 6 2 5 6 b When using Asynchronous Mode INAS pin H SDTI1 SEL JP5 Asynchronous Synchronous GND SDTI2 SEL JP6 Asynchronous Synchronous GND SDTI3 SEL JP7 Asynchronous...

Page 8: ...4114 U6 a When using X Tal X1 In this case X Tal X2 is open JP52 EXT CLK DIT OMCKO SEL JP51 3 2 4 AK4128 EXT JP45 DIT OMCLK SEL DIT DSP5 EXT 2 5 6 JP53 SEL3 3 GND OMCLK JP20 MCKO b When using X Tal X2 In this case X Tal X1 is open JP52 EXT CLK DIT OMCKO SEL JP51 3 2 4 AK4128 EXT JP45 DIT OMCLK SEL DIT DSP5 EXT 2 5 6 JP53 SEL3 3 GND OMCLK JP20 MCKO c When using J8 EXT CLK In this case X Tal X1 and ...

Page 9: ...IT Slave DIT Master 2 3 4 2 3 4 JP18 AK4128 OBICK SEL JP19 AK4128 OLRCK SEL AK4128 Slave AK4128 Master AK4128 Slave AK4128 Master 2 3 4 2 3 4 2 1 3 2 When using OBICK OLRCK and SDTO of AK4128A U1 JP4 8 O BIC K JP4 9 S D T O JP5 0 O L R C K JP46 DIT OBICK SEL JP47 DIT OLRCK SEL DIT Slave DIT Master DIT Slave DIT Master 2 3 4 2 3 4 JP18 AK4128 OBICK SEL JP19 AK4128 OLRCK SEL AK4128 Slave AK4128 Mast...

Page 10: ...ks are fed through the 10pin port PORT5 2 2 1 Setup TX As Optical connector PORT10 OPT and BNC connector J5 COAX are not used please don t connect anything 2 2 2 Setup the OBICK OLRCK and SDTO 2 2 2 1 When using OBICK and OLRCK of 10pin port and SDTO of AK4128A U1 JP4 8 O BIC K JP4 9 S D T O JP5 0 O L R C K JP46 DIT OBICK SEL JP47 DIT OLRCK SEL DIT Slave DIT Master DIT Slave DIT Master 2 3 4 2 3 4...

Page 11: ...ster 2 3 4 2 3 4 JP 18 A K4128 OB ICK S EL JP19 A K4128 OLRCK SE L A K4128 Slav e A K4128 M aster AK 4128 Slave AK 4128 Master 2 3 4 2 3 4 2 2 2 3 Selection of SDTO1 SDTO2 SDTO3 and SDTO4 a Select to SDTO1 b Select to SDTO2 c Select to SDTO3 d Select to SDTO4 SD T O SEL JP1 7 2 3 4 2 ７ ８ SDTO 1 SD TO SE L JP 1 7 2 3 4 2 ７ ８ SDTO 1 SD TO SE L J P1 7 2 3 4 2 ７ ８ SDTO 1 S D TO SE L JP1 7 2 3 4 2 ７ ８ ...

Page 12: ...ult GND Connect to GND JP14 IBICK4 SEL The selection of input signal to IBICK4 pin IBICK4 Connect to BICK4 signal of DIR or 10 pin PORT Default GND Connect to GND JP15 SEL2 The selection of input signal to INAS pin INAS Connect to INAS signal Default GND Connect to GND JP16 UNLOCK The selection of connection to UNLOCK pin and LE1 OPEN Unconnection SHORT Connection Default JP21 TST0 The selection o...

Page 13: ...128A A KM104301 2010 09 13 JP31 EXT CLK The selection of J7 EXT CLK connector OPEN J7 EXT CLK connector is use SHORT J7 EXT CLK connector is not use Default If JP31 EXT CLK is set to OPEN JP27 is set to EXT ...

Page 14: ...Mode L 5 TST1 L 6 TST2 TEST Pin Fixed to L L 7 SMSEMI Semi auto Mode Manual Mode L 8 CAD0 Chip Address 0 bit 1 Chip Address 0 bit 0 L Table 2 SW3 Setting Mode IDIF2 pin IDIF1 pin IDIF0 pin SDTI1 4 Format IBICK Freq 0 L L L 16bit LSB justified 32FSI 1 L L H 20bit LSB justified 40FSI 2 L H L 24bit MSB justified 48FSI Default 3 L H H 24 16bit I2 S Compatible 48FSI or 32FSI 4 H L L 24bit LSB justified...

Page 15: ...ault 3 L H H I2 S Compatible 4 L L 5 L H Reserved 6 H L TDM256 mode 24bit MSB justified 7 H H H TDM256 mode 24bit I2 S Compatible Table 5 Output PORT Audio Interface Format Setting 1 OBICK Frequency Mode TDM pin Master Slave setting OBIT1 pin OBIT0 pin SDTO 1 4 OLRCK OBICK MSB justified I2 S LSB justified 0 L L 16bit 32FSO 1 L H 18bit 36FSO 2 H L 20bit 40FSO 3 Slave CM2 0 HLL or HHL H H 24bit Inpu...

Page 16: ...lave Bypass Mode Control Setting 1 3 SW5 setting Upper side is H and lower side is L SW4 No Name ON H OFF L Default 1 INAS Asynchronous mode Synchronous mode L 2 DITHER Dither ON Dither OFF L 3 SMT1 L 4 SMT0 Soft Mute Timer Setting Refer to Table 9 L 5 DEM0 H 6 DEM1 De emphasis Filter Setting Refer to Table 10 L 7 PM2 H 8 PM1 Channel Mode Setting Refer to Table 11 L Table 8 SW5 Setting SMT1pin SMT...

Page 17: ... down to VSS2 5 L H H 4 channel mode Power down Input Hi z Hi z H L L Power down Pull down to VSS2 5 Hi z L H L H 8 channel mode Normal operation Input Output Normal operation Default H H L H H H Not available Table 11 Channel Mode Setting 1 4 SW17 setting Upper side is H and lower side is L SW17 No Name ON H OFF L Default 1 TST3 L 2 TST0 TEST Pin Fixed to L L Table 12 SW17 Setting ...

Page 18: ...o Table 17 L 3 DIR2 DIF0 24bit I2 S Compatible 24bit Left justified L Table 14 SW7 Setting SW8 No Name ON H OFF L Default 1 DIR3 OCKS1 H 2 DIR3 OCKS0 Master Clock Frequency Setting Refer to Table 17 L 3 DIR3 DIF0 24bit I2 S Compatible 24bit Left justified L Table 15 SW8 Setting SW9 No Name ON H OFF L Default 1 DIR4 OCKS1 H 2 DIR4 OCKS0 Master Clock Frequency Setting Refer to Table 17 L 3 DIR4 DIF0...

Page 19: ...6fs 96 kHz 1 L H 256fs 96 kHz 2 H L 512fs 48 kHz Default 3 H H 128fs 192 kHz Table 19 Master Clock Frequency Setting LRCK BICK Mode DIF2 pin DIF1 pin DIF0 pin DAUX Format I O I O 0 L L L 24bit Left justified H L O 64fs O 1 L L H 24bit Left justified H L O 64fs O 2 L H L 24bit Left justified H L O 64fs O 3 L H H 24bit Left justified H L O 64fs O 4 H L L 24bit Left justified H L O 64fs O Default 5 H...

Page 20: ...p H during normal operation The AK4114 U3 should be resets once bringing L upon power up Keep L when AK4114 U3 is not used SW12 DIR3 PDN Resets the AK4114 U4 Keep H during normal operation The AK4114 U4 should be resets once bringing L upon power up Keep L when AK4114 U4 is not used SW13 DIR4 PDN Resets the AK4114 U5 Keep H during normal operation The AK4114 U5 should be resets once bringing L upo...

Page 21: ...ed via the printer port parallel port of IBM AT compatible PC Connect PORT1 CTRL with PC by 10 wire flat cable packed with the AKD4128A A 2 9 10 Connect 10pin Header PC Red 10 wire flat Cable PORT 11 uP I F SCL SDA SDA ACK AKD4128A A Figure 1 Connection of 10 wire flat cable ...

Page 22: ...irection of the 10pin header When running this control soft on the Windows 2000 XP the driver which is included in the CD must be installed Refer to the Driver Control Install Manual for AKM Device Control Software for installing the driver When running this control soft on the windows 95 98 ME driver installing is not necessary This control soft does not support the Windows NT 3 Proceed evaluatio...

Page 23: ...zing When the device is reset by a hardware reset use this button to initialize the registers 3 All Write Executing write commands for all registers displayed 4 All Read Executing read commands for all registers displayed 5 Save Saving current register settings to a file 6 Load Executing data write from a saved file 7 All Req Write All Req Write dialog box is popped up 8 Data R W Data R W dialog b...

Page 24: ...er writings Writings are executed in descending order Help Help window is popped up Save Saving the register setting file assignment The file name is mar Open right Opening a saved register setting file assignment mar Close Closing the dialog box and finish the process Operating Suggestions 1 Those files saved by Save button and opened by Open button on the right of the dialog mar should be stored...

Page 25: ...dress in hexadecimal numbers for data writing Data Box Input data in hexadecimal numbers Mask Box Input mask data in hexadecimal numbers This is AND processed input data Write Writing to the address specified by Address box Close Closing the dialog box and finish the process Data writing can be cancelled by this button instead of Write button The register map will be updated after executing Write ...

Page 26: ... down menu No_use Not using this address Register Register writing Reg Mask Register writing Masked Interval Taking an interval Stop Pausing the sequence End Finishing the sequence 2 Input sequence Address Data address Data Writing data Mask Mask Data box data is ANDed with Mask box data This is the actual writing data When Mask 0x00 current setting is hold When Mask 0xFF the 8bit data which is se...

Page 27: ... file name is aks Open Opening a sequence setting file aks Close Closing the dialog box and finish the process Stop of the sequence When Stop is selected in the sequence processing is paused and it starts again when Start button is clicked Restarting step number is shown in the Start Step box When finishing the process until the end of sequence Start Step will return to 1 The sequence can be start...

Page 28: ...s are executed in descending order Help Pop up the help window Save Saving sequence setting file assignment The file name is mas Open right Opening a saved sequence setting file assignment mas Close Closing the dialog box and finish the process Operating Suggestions 1 Those files saved by Save button and opened by Open button on the right of the dialog mas should be stored in the same folder 2 Whe...

Page 29: ...on switch Button Down indicates H or 1 and the bit name is in red when read only it is in deep red Button Up indicates L or 0 and the bit name is in blue when read only it is in gray Grayout registers are Read Only registers They can not be controlled The registers which is not defined in the datasheet are indicated as Figure 9 Window of REG ...

Page 30: ...rite setting value to the registers or click Cancel to cancel this setting Figure 10 Window of Register Set Read Data Read Click Read button located on the right of the each corresponded address to execute register reading After register reading the display will be updated regarding to the register status Button Down indicates H or 1 and the bit name is in red when read only it is in deep red Butt...

Page 31: ... AKD4128A A KM104301 2010 09 31 2 Tool Testing Tools This tab screen is for evaluation testing tool Click buttons for each testing tool Figure 11 Window of Tool ...

Page 32: ...at Test Repeat Test Dialog Click Repeat Test button to open repeat test setting dialog box Figure 12 Window of Repeat Test Loop Setting Loop Setting Dialog Click Loop Setting button to open loop setting dialog box Figure 13 Window of Loop ...

Page 33: ...O FSI 48kHz 192kHz 133 3 133 4 133 5 133 3 133 3 133 4 133 4 133 5 dB FSO FSI 192kHz 48kHz 124 9 124 9 124 7 124 9 124 9 124 9 124 9 124 9 dB Worst Case FSO FSI 32kHz 176 4kHz 130 4 130 4 130 3 130 3 130 4 130 4 130 4 130 4 dB Dynamic Range Input 1kHz 60dBFS FSO FSI 44 1kHz 48kHz 136 5 136 5 136 7 136 7 136 7 136 9 136 8 136 8 dB FSO FSI 48kHz 44 1kHz 136 7 136 8 136 6 136 7 136 6 136 8 136 8 136 ...

Page 34: ...k 10k Hz 200 0 190 180 170 160 150 140 130 120 110 100 90 80 70 60 50 40 30 20 10 d B F S Figure14 FFTPlot Input 0dBFS AKM AK4128A FFT AVDD DVDD 3 3V FSO FSI 44 1kHz 48kHz 1kHz 60dBFS Input 20 20k 50 100 200 500 1k 2k 5k 10k Hz 200 0 190 180 170 160 150 140 130 120 110 100 90 80 70 60 50 40 30 20 10 d B F S Figure15 FFTPlot Input 60dBFS ...

Page 35: ... 50 40 30 20 10 dBFS 150 120 148 146 144 142 140 138 136 134 132 130 128 126 124 122 d B F S Figure16 THD Nvs InputLevel AKM AK4128A THD N vs Input Frequency AVDD DVDD 3 3V FSO FSI 44 1kHz 48kHz 0dBFS Input 20 20k 50 100 200 500 1k 2k 5k 10k Hz 150 90 145 140 135 130 125 120 115 110 105 100 95 d B F S Figure17 THD Nvs InputFrequency Input 0dBFS ...

Page 36: ...00 200 500 1k 2k 5k 10k Hz 150 90 145 140 135 130 125 120 115 110 105 100 95 d B F S Figure18 THD Nvs InputFrequency Input 60dBFS AKM AK4128A Linearity AVDD DVDD 3 3V FSO FSI 44 1kHz 48kHz fin 1kHz 140 0 130 120 110 100 90 80 70 60 50 40 30 20 10 dBFS 150 0 140 130 120 110 100 90 80 70 60 50 40 30 20 10 d B F S Figure19 Linearity ...

Page 37: ... Hz 8 1 7 5 7 6 5 6 5 5 5 4 5 4 3 5 3 2 5 2 1 5 1 0 5 0 0 5 d B F S Figure 20 Frequency Response FSO 44 1kHz AKM AK4128A Frequency Response Blue FSI 48kHz Red FSI 96kHz Green FSI 192kHz AVDD DVDD 3 3V FSO 48kHz 0dBFS Input 2k 24k 4k 6k 8k 10k 12k 14k 16k 18k 20k 22k Hz 8 1 7 5 7 6 5 6 5 5 5 4 5 4 3 5 3 2 5 2 1 5 1 0 5 0 0 5 d B F S Figure 21 Frequency Response FSO 48kHz FSI 192kHz FSI 96kHz FSI 48...

Page 38: ...AKM As used here Note1 A critical component is one whose failure to function or perform may reasonably be expected to result whether directly or indirectly in the loss of the safety or effectiveness of the device or system containing it and which must therefore meet very high standards of performance and reliability Note2 A hazard related device or system is one designed or intended for life suppo...

Page 39: ...8A U1 AK4128A IBICK2 1 IMCLK 2 ILRCK1 3 IBICK1 4 DVDD 5 VSS2 6 SDTI4 7 SDTI1 8 SDTI2 9 SDTI3 10 IDIF0 11 IDIF1 12 IDIF2 13 ILRCK3 14 IBICK3 15 ILRCK4 16 IBICK4 17 INAS 18 UNLOCK 19 DVDD 20 VSS3 21 SMUTE 22 DITHER 23 PDN 24 SMT0 25 SMT1 26 DEM0 27 DEM1 28 PM1 29 OBIT0 30 OBIT1 31 PM2 32 TDM 33 CM2 34 CM1 35 CM0 36 ODIF1 37 ODIF0 38 SDTO3 39 SDTO2 40 SDTO1 41 SDTO4 42 VSS4 43 DVDD 44 OBICK 45 OLRCK ...

Page 40: ...R52 51 J1 BNC R PC J1 BNC R PC 1 2 3 4 5 JP27 IMCLK SEL JP27 IMCLK SEL R48 220k R48 220k JP26 INPUT1 SEL JP26 INPUT1 SEL C112 10u C112 10u J7 BNC R PC J7 BNC R PC C114 0 1u C114 0 1u C117 10u C117 10u C115 0 47u C115 0 47u JP28 JP28 C26 10u C26 10u JP30 JP30 C25 0 1u C25 0 1u R43 220k R43 220k JP31 JP31 PORT1 A1 10PA 2 54DSA PORT1 A1 10PA 2 54DSA 1 3 5 7 9 10 8 6 4 2 R44 220k R44 220k R47 51 R47 5...

Page 41: ... C118 0 1u R58 51 R58 51 JP35 JP35 R21 51 R21 51 R56 51 R56 51 R53 220k R53 220k C120 10u C120 10u PORT7 TORX141 PORT7 TORX141 OUT 1 VCC 3 GND 2 J2 BNC R PC J2 BNC R PC 1 2 3 4 5 R55 220k R55 220k R26 75 R26 75 C125 10u C125 10u C31 0 1u C31 0 1u L3 47u L3 47u 1 2 R54 220k R54 220k JP34 JP34 C123 0 47u C123 0 47u C28 10u C28 10u C27 0 1u C27 0 1u R59 51 R59 51 PORT2 A1 10PA 2 54DSA PORT2 A1 10PA 2...

Page 42: ... JP38 C126 0 1u C126 0 1u C32 10u C32 10u JP39 JP39 C29 0 1u C29 0 1u C129 0 1u C129 0 1u R72 51 R72 51 JP36 INPUT3 SEL JP36 INPUT3 SEL R73 51 R73 51 R57 220k R57 220k C132 10u C132 10u R60 220k R60 220k R51 18k R51 18k JP37 JP37 R32 51 R32 51 C130 0 47u C130 0 47u PORT8 TORX141 PORT8 TORX141 OUT 1 VCC 3 GND 2 C127 10u C127 10u J3 BNC R PC J3 BNC R PC 1 2 3 4 5 U4 AK4114 U4 AK4114 IPS0 1 NC 2 DIF0...

Page 43: ...0 1u C34 0 1u C136 0 1u C136 0 1u R79 51 R79 51 JP40 INPUT4 SEL JP40 INPUT4 SEL R80 51 R80 51 R75 220k R75 220k C139 10u C139 10u R76 220k R76 220k R74 18k R74 18k JP41 JP41 R34 51 R34 51 C137 0 47u C137 0 47u PORT9 TORX141 PORT9 TORX141 OUT 1 VCC 3 GND 2 J4 BNC R PC J4 BNC R PC 1 2 3 4 5 C134 10u C134 10u U5 AK4114 U5 AK4114 IPS0 1 NC 2 DIF0 3 TEST2 4 DIF1 5 NC 6 DIF2 7 IPS1 8 P SN 9 XTL0 10 XTL1...

Page 44: ...TPUT SEL JP44 OUTPUT SEL PORT5 A1 10PA 2 54DSA PORT5 A1 10PA 2 54DSA 1 3 5 7 9 10 8 6 4 2 C58 10u C58 10u U6 AK4114 U6 AK4114 IPS0 1 NC 2 DIF0 3 TEST2 4 DIF1 5 NC 6 DIF2 7 IPS1 8 P SN 9 XTL0 10 XTL1 11 TVDD 13 DVSS 14 TX0 15 TX1 16 BOUT 17 COUT 18 UOUT 19 VOUT 20 DVDD 21 DVSS 22 MCKO1 23 BICK 26 MCKO2 27 DAUX 28 XTO 29 XTI 30 PDN 31 CM0 32 CM1 33 OCKS1 34 OCKS0 35 INT0 36 AVDD 38 R 39 VCOM 40 AVSS...

Page 45: ...D4128A A A3 7 10 Tuesday August 24 2010 Title Size Document Number Rev Date Sheet of Buffer 0 AKD4128A A A3 7 10 Tuesday August 24 2010 Title Size Document Number Rev Date Sheet of Buffer 0 AKD4128A A A3 7 10 Tuesday August 24 2010 U11 74LVC541A U11 74LVC541A A1 2 A2 3 A3 4 A4 5 A5 6 A6 7 A7 8 A8 9 G1 1 G2 19 Y1 18 Y2 17 Y3 16 Y4 15 Y5 14 Y6 13 Y7 12 Y8 11 VCC 20 GND 10 U13 74LVC541A U13 74LVC541A...

Page 46: ... U8 74HC14 GND 7 1A 1 3A 5 5A 11 5Y 10 3Y 6 1Y 2 2Y 4 4Y 8 6Y 12 6A 13 4A 9 2A 3 VCC 14 SW13 ATE1D 2M3 SW13 ATE1D 2M3 2 1 3 C36 0 1u C36 0 1u D1 HSU119 D1 HSU119 K A R30 10k R30 10k C50 0 1u C50 0 1u C49 0 1u C49 0 1u R61 100 R61 100 C22 0 1u C22 0 1u U9 74HC14 U9 74HC14 GND 7 1A 1 3A 5 5A 11 5Y 10 3Y 6 1Y 2 2Y 4 4Y 8 6Y 12 6A 13 4A 9 2A 3 VCC 14 R28 10k R28 10k R69 10k R69 10k C48 0 1u C48 0 1u R...

Page 47: ...KS1 OBIT1 47k TDM ODIF1 CM1 CM2 ODIF0 CM0 OBIT0 INAS PM2 47K PM1 SMT1 DITHER DEM0 SMT0 DEM1 47K CAD0 IDIF0 SMSEMI TST1 SPB TST2 IDIF1 DIR2 DIF0 DIR2 OCKS0 DIR2 OCKS1 DIR3 DIF0 DIR3 OCKS0 DIR3 OCKS1 DIR4 DIF0 DIR4 OCKS0 DIR4 OCKS1 DIT DIF0 DIT OCKS0 DIT OCKS1 DIT DIF2 DIT DIF1 TST0 TST3 RP9 47k RP9 47k 5 4 3 2 1 RP4 RP4 9 8 7 6 5 4 3 2 1 SW9 A6E 3104 SW9 A6E 3104 6 5 4 1 2 3 SW6 A6E 3104 SW6 A6E 31...

Page 48: ... 10 Tuesday August 24 2010 AVDD REG DVDD REG GND1 GND2 GND3 GND4 D3 3V 1 REG D3 3V 2 REG C67 47u C67 47u T1 LT1117 3 3 T1 LT1117 3 3 GND 1 OUT 2 IN 3 C43 47u C43 47u JP2 DVDD SEL JP2 DVDD SEL C42 0 1u C42 0 1u TP33 TP33 TP32 TP32 TP34 TP34 TP31 TP31 C41 0 1u C41 0 1u C38 47u C38 47u C47 47u C47 47u C46 47u C46 47u C66 0 1u C66 0 1u JP4 D3 3V 2 SEL JP4 D3 3V 2 SEL JP1 AVDD SEL JP1 AVDD SEL T2 LT111...

Page 49: ...AK4128A A Rev 0 部品面シルク図 AKD4128A A Rev 0 Evaluation Board ...

Page 50: ...AK4128A A Rev 0 半田面シルク図 ...

Page 51: ...AK4128A A Rev 0 部品面パターン図 ...

Page 52: ...AK4128A A Rev 0 半田面パターン図 ...

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