Aiwa XD-DV170, Service Manual

Page: 40 / 53

-40-
Pin No. Pin Name I/O Description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35 ~ 42
43 ~ 50
51
52
53
54
55
IC DESCRIPTION - 4/8 (LC87F72C8A)-1/2
SUBRXD
SUBSCK
LEDD1
LEDCSB
LEDCLK
RDY_HIF
PWM
RESET
XT1/AN10
XT2/AN11
GND
CLOCK
CLOCK
+5V
TESTKEY
BUSYB
FBUSYB
HEXKEY
P84/AN4
OPEN_SW
CLOSE_SW
LSW
HIRQB
INT_SUBSCK
FGO
WRQ
S0/PA0
FEL_CSBI
FEL_CSBO
ZWR
ZRD
S5/PA5
WAITB
S7/PA7
DB0 ~ 7
AB0 ~ 7
+5V
GND
S24/PD0
DEFINHB
TOPEN
I
I
O
O
O
O
O
I
I
I/O
—
I
O
—
O
I
I
O
O
O
O
I
I
I
I
I
O
O
O
O
O
O
I
I/O
I/O
O
—
—
O
O
I
DATA input terminal for LOADER serial communication control.
Clock input terminal for LOADER serial communication control.
Detection of LEDD1.
Detection of LEDCSB.
Detection of LEDCLK.
LOADER READY signal output terminal.
Detection of PWM.
Reset signal input terminal.
Input for 32.768kHz crystal oscillation. AD input port: AN10. (Connected to power supply)
Out put for crystal oscillation. AD input port: AN11. (Not Connected)
GND.
In put for 10MHz crystal oscillation.
Out put for 10MHz crystal oscillation.
Power supply 5V.
TESTKEY output pin.
DSP command dispose busy signal input pin.
DSP command receiver busy signal input pin.
Detection of HEXKEY.
Detection of P84/AN4.
Detection of OPEN SW.
Detection of CLOSE SW pin.
LIMIT SW input pin.
Interrupt signal input pin.
Clock input terminal for LOADER serial communication control.
SENSER input.
Subcode Q read ready monitor input.
LCD display segment output. (Not Connected)
Chip select signal output pin.
Chip select signal output pin.
Write signal output pin.
Read signal output pin.
FECONT control output pin.
Wait signal input pin.
Detection of S7/PA7.
Data 0 ~ 7.
Address 0 ~ 7.
Power supply 5V.
GND.
Detection of S24/PD0.
DEFINHB control output.
RF general-purpose port output pin 0.