Aiwa AM-HX50, Service Manual

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26
________
WE signal output terminal to DRAM.
Data input/output terminal to DRAM.
_________
CAS signal output terminal to DRAM.
______
OE signal output terminal to DRAM.
Address output terminal to DRAM.
Monitor signal output terminal.
Frame sync detection signal output terminal. Low: sync, Hi: sync NG.
CLV servo lock detection output terminal.
Focus OK signal output terminal.
Defect signal input/output terminal.
4.2336 MHz/8.4672 MHz output terminal.
Internal power supply terminal.
Ground terminal.
Power supply terminal.
Data transfer clock input terminal for CPU interface.
Chip enable signal input terminal for CPU interface.
Data input terminal for CPU interface.
Data output terminal for CPU interface.
Interrupt signal output terminal for CPU interface.
Wobble signal input terminal.
Test input terminal.
VCEC system clock signal output terminal.
Power supply terminal for VCEC.
The terminal to which external bias resistor setting oscillation frequency of VCEC is
connected.
The terminal to which external bias resistor setting current charge pump of VCEC is
connected.
Ground terminal for VCEC.
Current charge pump output terminal of VCEC.
Input terminal for test.
O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I/O
O
—
—
—
I
I
I
O
O
O
I
I
O
—
I
I
—
O
I
MWEB
MD1
MD0
MD3
MD2
MCASB
MOEB
MAD8
MAD7
MAD6
MAD5
MAD4
SMON3
SMON2
SMON1
SMON0
FSEQ
VP
FOK
DEFECT
UCLK
VDD1
VSS
VDD2
CL
CE
DI
DO
WRQB
INTB
ADIPWO
RCUT
PCK
VCVDD
FR
ISET
VCVSS
PDO
TEST3
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
Pin No. Pin Name I/O Description