–
20
–
43
SPPWMF
O
Spindle PWM output.
44
SPPWMR
O
Spindle PWM output.
45
SLPWMF
O
Sled PWM output.
46
MAD2
O
DRAM address output.
47
SLPWMR
O
Sled PWM output.
48
MAD1
O
DRAM address output.
49
FOPWMF
O
Focus PWM output.
50
MAD0
O
DRAM address output.
51 FOPWMR O Focus PWM output.
52
TRPWMF
O
Tracking PWM output.
53 TRPWMR O Tracking PWM output.
54 MAD10 O DRAM address output.
55 AVDD - 1bit D/C converter power supply.
56
OUTL
O
1bit D/C converter left channel output.
57
OUTR
O
1bit D/C converter Right channel output.
58
AVSS
O
1bit D/C converter ground.
59
VDD2
–
Power supply.
60
XIN
I
16.9344MHz oscillator circuit input.
61
XOUT
O
16.9344MHz oscillator circuit input.
62
VSS
–
GND.
63
VDD1
–
Power supply.
64
F16M
I
16.9344MHz circuit input.
65
ENH
O
De-emphasis indicator output.
66
LRCO
O
LR clock output.
67
DDATA
O
Expanded audio data output.
68
BCO
O
Bit clock output.
69
DDOUT
O
Digital audio output.
70
SMON3
O
Monitor signal output.
71
SMON2
O
Monitor signal output.
72
SMON1
O
Monitor signal output.
73
SMON0
O
Monitor signal output.
74
FSEQ
O
Frame period detection signal output.
75
VP
O
CLV servo lock recognition output.
76
MRASBT
O
Test output terminal.
77
MRASB
O
RAS signal output terminal to DRAM (Not connected).
78
FOK
O
Focus OK signal output terminal.
79
MWEB
O
WE signal output terminal to DRAM (Not connected).
80
DEFECT
O
Defect signal input and output terminal.
81
MD1
I/O
Data input and output terminal to DRAM (Not connected).
82
FG
I
Speed pulse input terminal.
83
CL
I
Data transfer clock input terminal for CPU interface.
84
CE
I
Chip enable signal input terminal for CPU interface.
Pin No.
Pin Name
I/O
Description
Summary of Contents for AM-CL33
Page 14: ... 14 SCHEMATIC DIAGRAM 1 MAIN ...
Page 16: ... 16 IC BLOCK DIAGRAM ...
