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APE1553-1/2(-DS) Hardware Manual
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TECHNICAL DATA
PCI Express bus:
Compatible with PCI-Express Standard (Release 1.1)
3.3V PCI Express card
Single Lane PCI Express bus operation 2.5 Gbit/s
Memory:
128 Mbyte DDR2-RAM
1x SPI-Flash for FPGA
2x SPI-Flash for BIUs
BIU-Section:
Low power, high performance 32bit RISC Processor(s)
Encoder:
For each BIU, one Manchester Encoder with Parity generator and
error injection.
-
Single implementation with bus switching logic
(not redundant for PRI- and SEC-MILbus)
-
Response time support via eight bit timer with 250ns resolution
Error Injection:
-
Parity error on selected word
-
SYNC pattern definable on half bit basis on selectable word
-
Manchester stuck at low or high error in selected word and bit
position
-
Gap error between selected words for 0.5 to 7.5 µs in 0.5µs
steps
-
Bit count error on selected word +/- 3 bits
Decoder:
For each BIU, one Manchester Decoder with Parity checker and
error detection.
-
Single implementation with bus switching logic (not redundant
for PRI- and SEC-MILbus).
-
Full error detection and indication
-
Interword gap and Response Time Measurement (<=100µs)
with 250ns resolution.