APE1553-1/2(-DS) Hardware Manual
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A Burst data memory is implemented in the FPGA, to store data in fast acquisition modes
(single shot, 50MSamples 2 busses or 100MSamples 1 bus), or used as a buffer in slower
acquisition modes (continues mode).
Notes:
50MSample-Mode means 49,5Msamples/s and 100Msample-Mode means 99MSamples/s
.
In 100MSample mode and in 50MSamples 2channel mode, the data storage is limited to
6kByte. In all other modes the storage range can be set
4.2
Implemented MILScope functions
A number of basic data analysis functions are implemented on the hardware (FPGA) and are
provided by software (see the MIL-STD-1553 Reference Manual).
4.2.1 Trigger Functions
•
Trigger type:
higher than
level sensitive trigger, trigger event when captured data is higher
than the trigger level
lower than
level sensitive trigger, trigger event when captured data is lower
than the trigger level
higher than for a given time, high pulse
trigger event when the captured data is higher than the trigger
level for a given time
lower than for a given time, low pulse
trigger event when the captured data is lower than the trigger
level for a given time
Bus Monitor
complex protocol trigger from the BIU Firmware
Note: The Trigger event might be delayed appr.10µs
•
Trigger Channel:
ch. A: the trigger source is channel A
ch. B: the trigger source is channel B
•
Sampling Rate:
10ns (one channel, 6kByte data queue size limitation)
20ns (two channels, 6kByte data queue size limitation)
20ns (one channel, data queue size is 16MByte
see Note
)
40ns (1 or 2 channels, data queue size is 16MByte
see Note
)
…
5,1µs (1 or 2 channels, data queue size is 16MByte
see Note
)
•
Trigger delay:
Delayed start of data acquisition after the trigger event
•
Trace before Trigger:
Data
captured
before the trigger event
Note: For some values a check of plausibility and a conversion from time to integer values
should be done by the Host software. For details see MIL-STD-1553 Reference Manual.
