9 - Remote Operation
33
QPX750 Instruction Manual
9.4.1
Standard Event Status and Standard Event Status Enable Registers
These two registers are implemented as required by the IEEE Std. 488.2.
Any bits set in the Standard Event Status Register which correspond to bits set in the Standard Event
Status Enable Register will cause the ESB bit to be set in the Status Byte Register.
The Standard Event Status Register is read and cleared by the *ESR? command. The Standard Event
Status Enable register is set by the *ESE<NRF> command and read by the *ESE? command.
It is a bit field where each bit has the following significance.
Bit 7
Power On. Set when power is first applied to the instrument.
Bit 6
Not used.
Bit 5
Command Error. Set when a syntax type error is detected in a command from the
bus. The parser is reset, and parsing continues at the next byte in the input
stream.
Bit 4
Execution Error. Set when an error is encountered while attempting to execute a
completely parsed command. The appropriate error number will be reported in
the Execution Error Register.
Bit 3
Verify Timeout Error. Set when a parameter is set with 'verify' specified and the
value is not reached within 5 secs, e.g., output voltage is slowed by a large
capacitor on the output.
Bit 2
Query Error. Set when a query error occurs. The appropriate error number will be
reported in the Query Error Register.
Bit 1
Not used.
Bit 0
Operation Complete: Set in response to the ‘*OPC’ command.
