38
Status Reporting
The standard status and error reporting model described in IEEE Std. 488.2 was designed for the
GPIB interface and contains some features intended for use with the Service Request and
Parallel Poll hardware capabilities of that interface, and to accommodate its semi-duplex
operation. Although those facilities are of little use with other interfaces, this instrument makes
the full set of capabilities available to all of the interfaces. A separate set of many of the status
and error registers is maintained for each potential interface instance. The GPIB, USB and
RS232 interfaces each provide a single instance, while the LAN interface provides three: one for
the Web page and one each for the two TCP socket interfaces. Having a separate status model
for each interface instance ensures that data does not get lost, as some status query commands
(e.g. ‘*ESR?’) clear the contents of a register after reading the present value.
The full set of error and status registers and the individual bits they contain is shown in the Status
Model Diagram and described in detail below, but in brief the status is maintained using four
primary registers, the Input State Register, the Input Trip Register, the Standard Event Status
Register and the Execution Error register. A summary is reported in the Status Byte Register, as
selected by three masking registers – the Input State Enable Register, the Input Trip Enable
register and the Standard Event Status Enable Register. Two further mask registers, the Service
Request Enable register and the Parallel Poll Response Enable register, control operation of the
GPIB hardware Service Request and Parallel Poll (and the associated
ist
message) respectively.
It is recommended that, when controlling the unit through any interface other than GPIB, the
controller program should simply read the primary status registers directly.
The instrument specific Input State and Input Trip Registers record events related to the electrical
function of the load and its interaction with the source under test.
The Standard Event Status Register, supported by the Execution Error and Query Error registers,
records events concerned with command parsing and execution, and the flow of commands,
queries and responses across the interface. These are mainly of use during software
development, as a production test procedure should never generate any of these errors.
Input State and Input Trip Registers (ISR & ISE and ITR & ITE).
These two registers report electrical conditions that have arisen during the operation of the load.
By their nature they are common to all interfaces.
The Input Trip Register reports events that have resulted in the unit unexpectedly disabling the
load input.
The Input State Register reports the present state of the power stage of the load in the same way
as the green and yellow lamps on the front panel and the status line of the display.
Each of these registers has a summary bit in the Status Byte Register, with an associated Enable
Register to determine which, if any, bits contribute to that summary. All these registers are bit
fields, where each bit is independent (so more than one may be set simultaneously) and has the
significance detailed below.
Input Trip Register (ITR)
Bit 7
Fault trip:
the input has been disabled by one of the hardware fault detectors.
Bits 6-3
Not used, permanently 0.
Bit 2
Over Current protect:
the input has been disabled because the current exceeded the
limit specified by the user.
Bit 1
Over Voltage protect:
the input has been disabled because the applied voltage
exceeded the limit specified by the user.
Bit 0
Over Power protect:
Set in 600W mode if the permitted power and time limit has been
exceeded by more than 10 seconds.
The bits in the Input Trip register are set when the event they report occurs, and then remain set
until read by the ITR? query. After the Response Message is sent any bits reporting conditions
