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Because of changes in the transconductance of the FETs, the dynamic behaviour of the power
stages changes at both low and high currents, and also at low voltages when the inter-electrode
capacitance increases considerably. In general, behaviour is optimum in the middle of the current
range (5 to 60 Amps) and at voltages between about 3 volts and (if there is significant source
impedance) about 3 volts below the open circuit voltage of the source.
Attempting to achieve a slew rate beyond the capabilities of a source and load combination can
result in substantial overshoot and ringing. Reducing the slew rate, sometimes by just a small
amount, will often improve the response considerably.
Source Characteristics
The purpose of transient testing is to examine the behaviour of any feedback loops within the
source. If the response of the source is under-damped, then in general the use of an active load
will accentuate the effect. This is particularly true in the modes where the load responds to
changes in voltage. At particular transient frequencies (particularly higher frequencies) the load
may excite resonances in L-C filters or match the natural frequency of a feedback loop. This can
result in considerable reaction from the source, possibly to the extent of causing damage.
Mechanical generators have substantial inductance, mechanical inertia and slow response times.
Transient response testing of such sources should only be attempted at low slew rates.
Start-up transients
There are two different start-up conditions to consider depending on whether the source or the
load is switched on first.
If the source is switched on first and the load enabled afterwards then the start-up may have a
small transient, but this will not generally exceed the magnitude of the Level setting, except at
very low current settings (below a few Amps). This transient can be controlled by selecting Slow
Start and setting a gentle Slew Rate.
In the other case, when the load is enabled before the source is switched on, much larger
transients can be generated. The reason for this is that as soon as the load is enabled the
internal feedback loop will attempt to conduct the current demanded by the level setting. In the
absence of a source voltage this will result in the gate drivers applying maximum bias voltage to
the power FETs, reducing their resistance to minimum (<25m
Ω
) in an attempt to force a current
to flow. This is the condition that produces the
Low Voltage
warning on the status line of the
display. When the source is switched on and starts to produce a voltage it will initially see this
25m
Ω
load, which will cause a significant current transient until the feedback loop has time to
respond and reduce the bias on the FETs. There are two means to reduce this. One is to use the
Slow Start facility with a non-zero setting of the Dropout Voltage to ensure that the load does not
attempt to conduct until the source voltage is present, and then set the Slew Rate to control the
initial transient. The second is to use Constant Resistance (CR) mode, when zero source voltage
should cause zero current to flow. Because of the tolerance on internal offset voltages it may be
necessary to set the Dropout Voltage to a small value (a few tens of mV) to ensure that the unit
does not enter the
Low Voltage
saturation condition (the yellow lamp also indicates this).
If it is desired to test the start-up behaviour of a power supply, the best approach is to use a small
auxiliary supply to pre-bias the load into conduction, together with series isolating diodes to
cause the load current to transfer from this bias supply to the supply under test when it starts to
produce its output voltage.
Characteristics of each Operating Mode
The following sections give a brief description of the way each mode is implemented, and give
some guidance of the effect that has on the application of the load.
The unit has two power stages (each a large FET) in parallel. Local current feedback around
each stage ensures equal power sharing, with overall current feedback to an earlier stage used
to enhance accuracy. This architecture provides fundamentally a constant current sink. Ideally
the operation of the power stages would be independent of the applied voltage, but in practice,
