Advantech PCM-9590, User Manual

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31 PCM-9590 User Manual
Chapter 3 BIOS Operation
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DRAM RAS# to CAS# Delay [Auto]
This item enables users to set the timing of the transition from RAS (row
address strobe) to CAS (column address strobe) as both rows and column are
separately addressed shortly after DRAM is refreshed.
„
DRAM RAS# Precharge [Auto]
This item enables users to set the DRAM RAS# precharge timing, system
default is setting to “Auto” to reference the data from SPD ROM.
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System BIOS Cacheable [Enabled]
This item allows the system BIOS to be cached to allow faster execution and
better performance.
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Video BIOS Cacheable [Disabled]
This item allows the video BIOS to be cached to allow faster execution and bet-
ter performance.
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Memory Hole At 15M-16M [Disabled]
This item reserves 15MB-16MB memory address space to ISA expansion cards
that specifically require the setting. Memory from 15MB-16MB will be unavail-
able to the system because of the expansion cards can only access memory at
this area.
3.2.5 Integrated Peripherals
Note! This “Integrated Peripherals” option controls the configuration of the
board’s chipset, includes IDE, ATA, SATA, USB, AC97, MC97 and
Super IO and Sensor devices, this page is developed by Chipset inde-
pendent.