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PCI-1751U User’s Manual

Appendix B Register Format

Base
A
(Decimal)

Function

Read

Write

Port A0

Port B0

Port C0

Port 0 Configuration Register

Port A1

Port B1

Port C1

Port 1 Configuration Register

8 ~ 19

Reserved

BoardID

Reserved

21~23

Reserved

8254 Counter 0

8254 Counter 1

8254 Counter 2

8254 Control Register

Reserved

Interrupt Status Register

Interrupt Control Register

Summary of Contents for PCI-1751U

Page 1: ...PCI 1751U 48 bit Digital Input Output Card with Universal PCI Bus User Manual ...

Page 2: ...d assumes no responsibility for its use nor for any infringements of the rights of third parties which may result from its use Acknowledgments PC LabCard is a trademark of Advantech Co Ltd IBM and PC are trademarks of International Business Machines Corporation MS DOS and Windows are trademarks of Microsoft Corporation Intel and Pentium are trademarks of Intel Corporation CE Notification The PCI 1...

Page 3: ...9 Table 2 1 Jumper Settings 9 2 4 Setting the BoardID Switch SW1 10 Table 2 2 BoardID Setting SW1 10 2 4 1 BoardID Register 10 Table 2 3 BoardID Register 10 2 5 PCI 1751U Block Diagram 11 Figure 2 2 PCI 1751U Block Diagram 11 2 6 Pin Assignments 12 2 7 Installation Instructions 13 Chapter 3 Operation 16 3 1 Introduction 16 3 2 Digital I O Ports 16 3 2 1 8255 Mode 0 16 3 2 2 Interrupt Function of t...

Page 4: ...t values 23 3 4 6 Interrupt Flag Bit 23 Table 3 5 Interrupt flag bit values 23 Appendix A Counter Chip Function 26 A 1 The Intel 8254 26 A 2 Counter Read Write and Control Registers 26 A 3 Counter Operating Modes 29 A 3 1 MODE 0 Stop on Terminal Count 29 A 3 2 MODE 1 Programmable One shot 29 A 3 3 MODE 2 Rate Generator 29 A 3 4 MODE 3 Square Wave Generator 30 A 3 5 MODE 4 Software Triggered Strobe...

Page 5: ...2 CHAPTER 1 General Information ...

Page 6: ...ble connections to field devices Two other features give the PCI 1751U practical advantages in an indus trial setting When the system is hot reset the power is not turned off the PCI 1751U retains the last I O port settings and output values if the user has set jumper JA1 to enable this feature Otherwise port settings and output values reset to their safe default state or to the state deter mined ...

Page 7: ... monitoring and control Relay and switch monitoring and control Parallel data transfer Sensing the signals of TTL DTL CMOS logic Driving indicator LEDs 1 1 4 Specifications I O channels 48 digital I O lines Programming mode 8255 PPI mode 0 1 1 5 Input Signal Logic high voltage 2 0 to 5 25 V Logic low voltage 0 0 to 0 80 V High level input current 20 mA Low level input current 0 2 mA 1 1 6 Output S...

Page 8: ...e and speed of computer Typical 1 MB sec tested under DOS Pentium 100 MHz CPU Maximum 1 5 MB sec Connector One SCSI II 68 pin female connector Power consumption 5 V 850 mA Typical 5 V 1 0 A Max Operating temperature 0 70º C 32º F 158 ºF Storage temperature 20 80º C 4º F 176º F Humidity 5 95 non condensing Dimension 170 x 100 mm 6 9 x 3 9 ...

Page 9: ...2 CHAPTER 2 Installation ...

Page 10: ...ill then make arrangements to repair or replace the unit 2 2 Unpacking The PCI 1751U contains components that are sensitive and vulnerable to static electricity Discharge any static electricity on your body to ground by touching the back of the system unit grounded metal before you touch the board Remove the PCI 1751U card from its protective packaging by grasping the card s rear panel Handle the ...

Page 11: ... identifying card components Figure 2 1 Connectors Jumpers 2 3 1 Set Ports as Input or Output by Software By shorting the upper two pins of jumpers JPA0 JPB0 JPC0L JPC0H JPA1 JPB1 JPC1L or JPC1H a user sets the corresponding ports to be configurable as input or output ports by software JPA0 means jumper for port A0 JPB0 means jumper for port B0 etc The initial state of each port after system power...

Page 12: ...d in the event of a hot reset the settings and output values present at the port just prior to reset are restored to each port following reset This feature applies to both ports set by software and to ports con figured as output ports via jumper Depending on the application this capability may allow a card to be reset without requiring a complete shut down of processes controlled by the card since...

Page 13: ...ng of Timer 0 and Timer 1 as a 32 bit timer Table 2 1 Jumper Settings Names of Jumpers Function description JPA0 JPA1 Jumpers for ports A0 A1 JPB0 JPB1 Jumpers for ports B0 B1 JPC0L JPC1L Jumpers for low nibble of ports C0 C1 JPC0H JPC1H Jumpers for high nibble of ports C0 C1 Sets port as an output port Sets port to be software configurable as input or output default JP1 Timer 0 P2 Timer 1 P3 Coun...

Page 14: ... 0 at the factory If you need to adjust this setting please see below 2 4 1 BoardID Register You can determine the BoardID setting in the register as shown below Table 2 2 BoardID Setting SW1 BoardID DEC Switch Position ID3 ID2 ID1 ID0 0 ON ON ON ON 1 ON ON ON OFF 2 ON ON OFF ON 3 ON ON OFF OFF 4 ON OFF ON ON 5 ON OFF ON OFF 6 ON OFF OFF ON 7 ON OFF OFF OFF 8 OFF ON ON ON 9 OFF ON ON OFF 10 OFF ON...

Page 15: ...11 Chapter2 2 5 PCI 1751U Block Diagram Figure 2 2 PCI 1751U Block Diagram ...

Page 16: ...O pins of Port C1 CNT0_OUT CNT1_OUT and CNT2_OUT Output pins of Counter Timer 0 1 and 2 CNT0_CLK CNT1_CLK and CNT2_CLK External clock source of Counter Timer 0 1 and 2 CNT0_G CNT1_G and CNT2_G Gate control pins of Counter Timer 0 1 and 2 INT_OUT Interrupt output This pin changes to logic 1 whenever PCI 1751U generates an interrupt and returns to logic 0 when the interrupt is cleared GND Ground VCC...

Page 17: ...ve the screw to secure the interface card retaining bracket 5 Carefully grasp the upper edge of the PCI 1751U Align the hole in the retaining bracket with the hole on the expansion slot and align the gold striped edge connector with the expansion slot socket Press the card into the socket gently but firmly Make sure the card fits the slot tightly 6 Secure the PCI 1751U by screwing the mounting bra...

Page 18: ...PCI 1751U User Manual 14 ...

Page 19: ...2 CHAPTER 3 Operation ...

Page 20: ... in mode 0 but with higher driving capability than a standard 8255 chip Each of the 8255 chips has 24 programmable I O pins that are divided into three 8 bit ports The total 48 DI O pins from both chips are divided into 6 ports designated PA0 PB0 PC0 PA1 PB1 and PC1 Each port can be programmed as an input or an output port The I O pins in port A0 are designated PA00 PA01 PA07 the pins in port B0 a...

Page 21: ...e output value has also been set An output voltage will appear at the pins immediately following the control word taking effect If no output value was specified the value will be indeterminate either 0 or 1 which may cause a dangerous condition 3 2 4 Initial Configuration The initial configuration of each port depends on the input output jumper setting of each port on the setting of the jumper JA1...

Page 22: ...r dry contact or 0 5 VDC wet contact inputs Dry contact capability allows the channel to respond to changes in external circuitry e g the closing of a switch in the external circuitry when no voltage is present in the external circuit Figure 3 1 shows external circuitry with both wet and dry contact components con nected as an input source to one of the card s digital input channels Figure 3 1 Wet...

Page 23: ...r more information on the operation modes of the counter chip The block diagram of the timer counter system is shown in Figure 3 2 Figure 3 2 Timer Counter Structure 3 3 2 Timer 0 1 Two 16 bit Timers or One 32 bit Timer Timer 0 and Timer 1 of the counter chip can be used separately or can be cascaded to create a 32 bit programmable timer by setting jumper JP2 By setting the clock source of Timer 1...

Page 24: ... an event counter Counter 2 is set as mode 0 interrupt on terminal count in the driver provided by Advantech 3 3 4 Timer Counter Frequency and Interrupt The input clock frequency of the counter timers is 10 MHz The output of both Timer 1 and Counter 2 can generate interrupts for the system refer to section 3 3 The maximum and minimum timer interrupt frequency is 10 MHz 2 5 MHz and 10 MHz 65535 655...

Page 25: ...e PCI plug and play BIOS and is saved in the PCI controller There is no need for users to set the IRQ level Only one IRQ level is used by this card although it has two inter rupt sources 3 4 3 Interrupt Control Register Base 32 The Interrupt Control Register Base 32 controls the interrupt signal source edge and flag Table 3 2 shows the bit map of the interrupt control register The register is a re...

Page 26: ... determine the interrupt source for port 1 as indicated in Figure 3 3 Table 3 3 shows the rela tionship between an interrupt source and the values in the mode bits Figure 3 3 Figure 3 3 Interrupt sources Table 3 3 Interrupt mode bit values Port 1 Port 0 M11 M10 Description M01 M00 Description 0 0 Disable interrupt 0 0 Disable interrupt 0 1 Source PC10 0 1 Source PC00 1 0 Source PC10 PC14 1 0 Sourc...

Page 27: ... flag indicating the status of an interrupt It is a readable and writable bit Read the bit value to find the status of the interrupt write 1 to this bit to clear the interrupt This bit must be cleared in the ISR to service the next incoming interrupt Table 3 4 Triggering edge control bit values E0 or E1 Triggering edge of interrupt signal 1 Rising edge trigger 0 Falling edge trigge Table 3 5 Inter...

Page 28: ...PCI 1751U User Manual 24 ...

Page 29: ...2 APPENDIX A Function of 8254 Counter Chip ...

Page 30: ...en the clock source of Timer 1 is set to be the output of Timer 0 inter nal source the two timers are cascaded as a 32 bit timer When the clock source of Timer 0 is provided externally by setting JP1 Timers 0 and 1 can be used as a 32 bit event counter Refer to section 2 3 3 for details of jumper settings A 2 Counter Read Write and Control Registers The 8254 programmable interval timer uses four r...

Page 31: ...1 RW0Select read write operation Operation RW1 RW0 Counter latch 0 0 Read write LSB 0 1 Read write MSB 1 0 Read write LSB first 1 1 then MSB M2 M1 M0Select operating mode M2 M1 M0 Mode 0 0 0 0 programmable one shot 0 0 1 1 programmable one shot X 1 0 2 Rate generator X 1 1 3 Square wave rate generator 1 0 0 4 Software triggered strobe 1 0 1 5 Hardware triggered strobe BCD Select binary or BCD coun...

Page 32: ... D2 D1 D0 Value 1 1 CNT STA C2 C1 C0 X CNT 0 Latch count of selected counter s STA 0 Latch status of selected counter s C2 C1 C0 Select counter for a read back operation C2 1 select Counter 2 C1 1 select Counter 1 C0 1 select Counter 0 If you set both SC1 and SC0 to 1 and STA to 0 the register selected by C2 to C0 contains a byte which shows the status of the counter The data format of the counter...

Page 33: ...erminal count If you load a new count value while the output is low the new value will not affect the duration of the one shot pulse until the succeed ing trigger You can read the current count at any time without affecting the one shot pulse The one shot is retriggerable thus the output will remain low for the full count after any rising edge at the gate input A 3 3 MODE 2 Rate Generator The outp...

Page 34: ...and the full count is reloaded The first clock pulse following the reload decrements the counter by 3 Subsequent clock pulses decrement the count by two until time out then the whole process is repeated In this way if the count is odd the output will be high for N 1 2 counts and low for N 1 2 counts A 3 5 MODE 4 Software Triggered Strobe After the mode is set the output will be high When the count...

Page 35: ...is command to the control word register The format is as shown at the beginning of this section The read back command can latch multiple counter output latches Sim ply set the CNT bit to 0 and select the desired counter s This single command is functionally equivalent to multiple counter latch commands one for each counter latched The read back command can also latch sta tus information for select...

Page 36: ... compatible programmable interval timer counter on your PCI 1751U interface card is a a very useful device You can program timers 1 and 2 to serve as timers event counters square wave generators or as a watchdog to generate regular interrupts at a fixed interval ...

Page 37: ...2 APPENDIX B Register Format of PCI 1751U ...

Page 38: ... 5 Port B1 Port B1 6 Port C1 Port C1 7 Port 1 Configuration Register 8 19 Reserved Reserved 20 BoardID Reserved 21 23 Reserved Reserved 24 8254 Counter 0 8254 Counter 0 25 8254 Counter 1 8254 Counter 1 26 8254 Counter 2 8254 Counter 2 27 8254 Control Register 28 Reserved Reserved 29 Reserved Reserved 30 Reserved Reserved 31 Reserved Reserved 32 Interrupt Status Register Interrupt Control Register ...

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