Advantech PCI-1751U, User Manual

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21 Chapter 3
3.4 Interrupt Function
3.4.1 Introduction
Two lines in each I/O port (C0 and C4) and two of the three counter out-
puts (Timer 1 and Counter 2) are connected to the interrupt circuitry. The
"Interrupt Control Register" of the PCI-1751U controls how the combina-
tion of the 6 signals generates an interrupt. Two interrupt request signals
can be generated at the same time, and then the software can service these
two request signals by ISR. The dual interrupt sources provide the card
with more capability and flexibility.
3.4.2 IRQ Level
The IRQ level is set automatically by the PCI plug and play BIOS and is
saved in the PCI controller. There is no need for users to set the IRQ
level. Only one IRQ level is used by this card, although it has two inter-
rupt sources.
3.4.3 Interrupt Control Register (Base + 32)
The "Interrupt Control Register" (Base + 32) controls the interrupt signal
source, edge and flag. Table 3-2 shows the bit map of the interrupt control
register. The register is a readable/writable register. When writing to it, it
is used as a control register, and when reading from it, it is used as a status
register.
M00 and M01: "mode bits" of port 0
M10 and M11: "mode bits" of port 1
E0, E1: triggering edge control bits
F0, F1: flag bits
Table 3.2: Interrupt control register bit map
Port # Port 1 Port 0
Bit # D7 D6 D5 D4 D3 D2 D1 D0
Abbreviation F1 E1 M11 M10 F0 E0 M01 M0