Advantech PCA-6181, Manual, Page: 49 / 126

Chapter 3 Award BIOS Setup 35
3.5.9 USB Mouse Support
Select Enabled if your system contains a Universal Serial Bus (USB)
controller and you have a USB mouse. The choice: Enabled, Disabled.
3.5.10 CPU to PCI Write Buffer
When this field is Enabled, writes from the CPU to the PCI bus are
buffered, to compensate for the speed differences between the CPU
and the PCI bus. When
Disabled , the writes are not buffered and the
CPU must wait until the write is complete before starting another write
cycle. The choice: Enabled, Disabled..
3.5.11 PCI Dynamic Bursting
When Enabled, every write transaction goes to the write buffer.
Burstable transactions then burst on the PCI bus and nonburstable
transactions don’t. The choice: Enabled, Disabled
3.5.12 PCI Master 0 WS Write
When Enabled, writes to the PCI bus are executed with zero wait
states. The choice: Enabled, Disabled
3.5.13 PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support
delay transactions cycles. Select
Enabled to support compliance with
PCI specification version 2.1. The choice: Enabled, Disabled
3.5.14 AGP Master 1 WS Write
When Enabled, writes to the AGP(Accelerated Graphics Port) are
executed with one wait states. The choice: Enabled, Disabled
3.5.15 Memory Parity/ ECC Check
Enabled add a parity check to the boot-up memory test. Select
Enabled when only system DRAM contains parity. The Choice:
Enable, Disable.