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MIC-5602 User Manual
Chapter 2
B
oard Specification
2.2
Product Features
2.2.1
CPU
The MIC-5602 supports the low wattage Intel Core 2 Duo LV and Core 2 Duo ULV
processors on 65 nm technology with core frequencies up to 1.5 GHz and 667 MHz
Front Side Bus (FSB). These processors are validated with the integrated Intel
server-class 3100 chipset. This chipset provides greater flexibility for developers of
embedded applications by integrating the memory and I/O control functions into a
single component, addressing the needs for high-performance, high-reliability, and
low-power consumption within a small form factor such as the MIC-5602. Current
supported processors are listed in the table below. The Intel Core 2 Duo L7400 pro-
cessor delivers 1.5 GHz of core frequency and 4 MB of L2 cache. It inherits a low
thermal design power of 17 W. And, the Intel Core 2 Duo U7500 processor offering
1.06 GHz of core frequency and 2 MB of L2 cache comes with ultra low maximum
heat dissipation of 10 W.
2.2.2
BIOS
An 8 Mbit Firmware Hub (FWH) contains a board-specific BIOS (from AMI) designed
to meet telecom and embedded system requirements. The device shall implement
boot sector protection and dual images to support BIOS update failure recovery. The
BIOS boot sector contains the early start-up code. Two BIOS images stored in the
non volatile memory are the "User" image (Default: Image 0) and the "Recovery"
image (Image 1). The program code in the boot sector will checksum the User image
and start the User BIOS if it has a valid checksum, otherwise it will boot the Recovery
BIOS image. The AMC Module also has a jumper (CN8) for forcing the BIOS into the
recovery mode (see Section 2.2.19).
Environment
Operating
Non-operating
Temperature
-5 ~ 55 °C (23 ~ 122 °F) -40 ~ 70 °C (-40 ~ 140 °F)
Humidity
IEC60068-2-78 (95%RH @ 40 °C)
Vibration
(5 ~ 500Hz)
IEC60068-2-6 (0.002 G2/Hz, 1 Grms)
Shock
IEC60068-2-27 (10 G, 11 ms)
Altitude
Sea level to 4,000 m
above sea level
10,000 above sea level
Regulatory
Conformance
UL94V0, FCC Class B, CE, RoHS & WEEE Ready
NEBS Level 3
Designed for GR-63-CORE and GR-1089-CORE
Compliance
Standards
PICMG AMC.0, AMC.1, AMC.2, AMC.3, IPMI v1.5,
HPM.1
Table 2.1: Advantech MIC-5602 Processor AMC Tech Data
Table 2.2: Intel Processor Selection for the MIC-5602
Model
Core Speed FSB Speed L2 Cache TDP
Package
Intel Core 2 Duo LV (L7400)
1.5 GHz
667 MHz
4 MB
17 W
uFCBGA
Intel Core 2 Duo ULV (U7500) 1.06 GHz
533 MHz
2 MB
10 W
uFCBGA
Summary of Contents for MIC-5602
Page 1: ...User Manual MIC 5602 Advanced Mezzanine Card Processor AMC...
Page 8: ...MIC 5602 User Manual viii...
Page 12: ...MIC 5602 User Manual xii...
Page 16: ...MIC 5602 User Manual 4...
Page 17: ...Chapter 2 2 Board Specification This chapter describes the hard ware features of the MIC 5602...
Page 33: ...Chapter 4 4 AMI BIOS Setup This chapter describes how to configure the AMI BIOS...
Page 44: ...MIC 5602 User Manual 32 Figure 4 13 Hard Disk Drives Figure 4 14 Removable Drives...
Page 51: ...Chapter 5 5 MMC Firmware Operation This chapter describes the MMC firmware features...
Page 66: ...MIC 5602 User Manual 54...
Page 67: ...Chapter 6 6 Overview of Supported Features and Known Limitations...
Page 71: ...Appendix A A IPMI PICMG Command Subset Supported by MMC...