Advantech MIC-3758DIO, User Manual

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MIC-3758DIO User Manual 24
4.2.1 Digital Filtering Example
The following figure shows a filter configuration with an 800 ns filter
interval (400 ns filter clock).
Figure 4.2: Digital Filter Example
In periods 1 and 2, the filter blocks the glitches because the external sig-
nal does not remain steadily high from one filter clock to the next. In
period 3, the filter passes the transition because the external signal
remains steadily high. Depending on when the transition occurs, the filter
may require up to two filter clocks—one full filter interval—to pass a
transition. The figure shows a rising (0 to 1) transition. The same filtering
applies to falling (1 to 0) transitions.
4.2.2 Digital Filter Function Control Register
There are two registers that control the digital filter function and status of
each channel: the Digital Filter Function Control Register and the Filter
Interval Time Preset Register. For details about their functions, please
refer to Appendix C.