Advantech MIC-3332, User Manual, Page: 8 / 62

MIC-3332 User Manual viii
Figure 2.5 Serial Console Setting.............................................. 17
Figure 2.6 USB configuration .................................................... 18
Figure 2.7 Virtualization............................................................. 19
Figure 2.8 Platform Management .............................................. 20
2.3.3 Hardware settings....................................................................... 21
Figure 2.9 Hardware BIOS Setup Screen ................................. 21
Figure 2.10CPU Configuration ................................................... 21
Figure 2.11Northbridge............................................................... 22
Figure 2.12Memory Configuration .............................................. 23
Figure 2.13PCI Subsystem......................................................... 23
Figure 2.14Southbridge .............................................................. 24
Figure 2.15SATA Configuration.................................................. 24
Figure 2.16NCT5523D Super IO Configuration.......................... 25
Figure 2.17Serial Port1 Configuration ........................................ 26
Figure 2.18NCT5523D H/W Monitor configuration..................... 26
Figure 2.19H/W Monitor configuration........................................ 27
Figure 2.20H/W Monitor configuration........................................ 27
2.3.4 Post & Boot................................................................................. 28
Figure 2.21Post & Boot Setup Screen........................................ 28
Figure 2.22CSM16 Parameters.................................................. 29
Figure 2.23CSM Parameters...................................................... 30
2.3.5 Security....................................................................................... 31
Figure 2.24Security Settings ...................................................... 31
2.3.6 Save & Exit ................................................................................. 32
Figure 2.25Save & Exit............................................................... 32
Appendix A Pin Assignments ............................... 35
A.1 J1 Connector........................................................................................... 36
Table A.1: J1 CompactPCI I/O .................................................. 36
A.2 J2 Connector........................................................................................... 37
Table A.2: J2 CompactPCI I/O .................................................. 37
Table A.3: VGA1 Connector ...................................................... 38
Table A.4: RJ45 LAN1/LAN2 Connector on 4HP board ............ 38
Table A.5: RJ45 LAN1/LAN2 Connector on 8HP XTM-1 Board &
RJ45 LAN1~LAN4 Connector on 8HP XTM-2 Board38
Table A.6: M12 LAN1/LAN2 Connector on 8HP XTM-1 Board &
M12 LAN1~LAN4 Connector on 8HP XTM-2 Board 39
Table A.7: USB3CN1(4HP), USB3CN2(4HP), USB3_CN1(8HP
XTM-1 Board)........................................................... 39
Table A.8: COM1 (RJ45) Connector on 8HP XTM-1 Board ...... 39
Table A.9: BAT_CN CMOS battery ........................................... 39
A.3 M/D, PWR, HDD, Hot-swap & LAN LEDs............................................... 40
Table A.10:Front Panel LEDs Indication..................................... 40
Appendix B Programming the Watchdog Timer . 41
Appendix C FPGA Specification ........................... 43
C.1 Overview ................................................................................................. 44
C.1.1 CPLD Functional Blocks............................................................. 44
Figure C.1 CPLD Block Diagram ............................................... 44
C.2 Features.................................................................................................. 44
C.3 FPGA I/O Registers ................................................................................ 45
Table C.1: Register Map ............................................................ 45
C.4 CPLD Upgrade........................................................................................ 48
C.4.1 JTAG Interface............................................................................ 48