Advantech iDAQ-900 Series, User Manual

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19 iDAQ-900 User Manual
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3.3.2 Buffered Analog Input Acquisition
With buffered analog input acquisition, the ADC conversion rate and the duration of
the acquisition is controlled by hardware timing signals. All conversion results are
sampled and stored in the buffer memory before sending back to the host computer
as shown in Figure 3.5.
Figure 3.5 Buffered analog input acquisition
The start and stop of the acquisition are controlled by the start trigger and stop trig -
ger, respectively. When configuration is completed, the acquisition engine of the
iDAQ chassis is at standby state. After receiving a start trigger, acquisition becomes
active and each rising edge of the sample clock acquires one analog input sample.
The acquisition active period lasts until a stop trigger is received, which ends the
acquisition. This is shown in Figure 3.6.
Figure 3.6 Start and stop of the analog input acquisition