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BASE+1
Interrupt Status Register (ISR) when DLAB=0
bit
0
Enable
received-data-available
interrupt
bit
1
Enable
transmitter-holding-register-empty
interrupt
bit
2
Enable
receiver-line-status
interrupt
bit 3
Enable modem-status interrupt
BASE+2
FIFO Control Register (FCR)
bit 0
Enable transmit and receive FIFOs
bit 1
Clear contents of receive FIFO
bit 2
Clear contents of transmit FIFO
bits
6-7
Set
trigger
level for receiver FIFO interrupt
Bit 7
Bit 6
FIFO trigger level
0 0 01
0 1 04
1 0 08
1 1 14
BASE+3
Line Control Register (LCR)
bit 0
Word length select bit 0
bit
1
Word
length
select
bit
1
Bit 1
Bit 0
Word length (bits)
0 0 5
0 1 6
1 0 7
1 1 8
bit 2
Number of stop bits
bit
3
Parity
enable
bit
4
Even
parity
select
bit
5
Stick
parity
bit
6
Set
break
bit 7
Divisor Latch Access Bit (DLAB)
BASE+4
Modem Control Register (MCR)
bit
0
DTR
bit
1
RTS
BASE+5 Line
Status
Register
(LSR)
bit
0
Receiver
data
ready
bit 1
Overrun error
bit 2
Parity error
bit
3
Framing
error
bit
4
Break
interrupt
bit
5
Transmitter
holding
register
empty
bit
6
Transmitter
shift
register
empty
bit 7
At least one parity error, framing error or break indication in the
FIFO
BASE+6
Modem Status Register (MSR)
bit
0
Delta
CTS
bit 1
Delta DSR
bit 2
Trailing edge ring indicator
bit 3
Delta received line signal detect
bit
4
CTS
bit
5
DSR
bit
6
RI
bit
7
Received
line
signal
detect
BASE+7
Temporary data register