ADLINK Technology Q7-BT, Technical Reference

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Interfaces 23
Q7-BT
147 GND 148 GND
149 D/TMD
(DisplayPort differential pair lines lane 0,
shared with TMDS differential pair lines
lane 2.) 150 HDMI_CTRL_DAT (DDC based control
signal [data] for HDMI
device.
Note: Level shifters must be implemented
on the carrier board for this signal in order
to be compliant with the HDMI
Specification.)
151 DP_LANE0-/TMDS_LANE2-
(DisplayPort differential pair lines lane 0,
shared with TMDS differential pair lines
lane 2.) 152 HDMI_CTRL_CLK (DDC based control
signal [clock] for HDMI
device.
Note: Level shifters must be implemented
on the carrier board for this signal in order
to be compliant with the HDMI
Specification.)
153 DP_HDMI_HPD# (Hot plug detection
signal that serves as an interrupt
request.) 154 RSVD
155 PCIE_ (PCI Express
Reference Clock for Lanes 0 to 3.) 156 PCIE_WAKE# (PCI Express Wake Event:
Sideband wake signal asserted by
components requesting wakeup.)
157 PCIE_CLK_REF- (PCI Express
Reference Clock for Lanes 0 to 3.) 158 PCIE_RST# (Reset Signal for external
devices.)
159 GND 160 GND
161 P (PCI Express channel 3,
Transmit Output differential pair.) 162 P (PCI Express channel 3,
Receive Input differential pair.)
163 PCIE3_TX- (PCI Express channel 3,
Transmit Output differential pair.) 164 PCIE3_RX- (PCI Express channel 3,
Receive Input differential pair.)
165 GND 166 GND
167 P (PCI Express channel 2,
Transmit Output differential pair.) 168 P (PCI Express channel 2,
Receive Input differential pair.)
169 PCIE2_TX- (PCI Express channel 2,
Transmit Output differential pair.) 170 PCIE2_RX- (PCI Express channel 2,
Receive Input differential pair.)
171 UART0_TX (Serial Data Transmitter) 172 UART0_RTS# (Handshake signal, ready to
receive data)
173 P (PCI Express channel 1,
Transmit Output differential pair.) 174 P (PCI Express channel 1,
Receive Input differential pair.)
175 PCIE1_TX- (PCI Express channel 1,
Transmit Output differential pair.) 176 PCIE1_RX- (PCI Express channel 1,
Receive Input differential pair.)
177 UART0_RX (Serial Data Receiver) 178 UART0_CTS# (Handshake signal, ready to
send data)
179 P (PCI Express channel 0,
Transmit Output differential pair.) 180 P (PCI Express channel 0,
Receive Input differential pair.)
181 PCIE0_TX- (PCI Express channel 0,
Transmit Output differential pair.) 182 PCIE0_RX- (PCI Express channel 0,
Receive Input differential pair.)
183 GND 184 GND
185 LPC_AD0 (Command, Address and Data
0 signal.) 186 LPC_AD1 (Command, Address and Data 1
signal.)
187 LPC_AD2 (Command, Address and Data
2 signal.) 188 LPC_AD3 (Command, Address and Data 3
signal.)
189 LPC_CLK (LPC clock.) 190 LPC_FRAME# (LPC frame indicates the
start of a new cycle or the termination of a
broken cycle.)
Table 3-1: Q7 Interface (GF1) Signal Descriptions (Continued)
Pin # Primary (Top Side) Pin # Secondary (Bottom Side)