Operation Theory
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latched. This ensures D/A conversions to be synchronized for
each channel in the same D/A group. Users can utilize this
property to perform multi-channel waveform generation without
any phase-lag.
Hardware controlled Waveform Generation
FIFO is a hardware first-in first-out data queue, which holds
temporary digital codes for D/A conversion. When DAQ/PXI-
2500 SERIES operates in Waveform Generation mode, the
waveform patterns are stored in FIFO, with 8K maximum sam-
ples. Waveform patterns larger than 8K are also supported by
utilizing bus-mastering DMA transfer supported by PCI con-
troller. Data format in FIFO is shown in Figure 4-7.
Figure 4-7: Data Format in FIFO and mapping
With hardware-based Waveform Generation, D/A conversions
are updated automatically by CPLD rather than application
software. Unlike the con-ventional Software-based Waveform
Generation, the precise hardware timing control guarantees
non-distorted waveform generation even when host CPU is