nanoX-AL
System Resources
39
IO APIC Pin
Routing
46 reserved
47 reserved
48 reserved
49 reserved
50 - 119
GPIO (Not for end user)
Note:
These IRQs can be used for PCI devices when onboard device is disabled.
APIC Mode
IRQ#
Typical Intterupt Resource
Connected to Pin
Available
0 Counter
0
N/A
No
1 Keyboard
controller
IRQ1 via SERIRQ
No
2
Cascade interrupt from slave PIC
N/A
No
3
Serial Port 4 (COM3)
IRQ3 via SERIRQ
Note (1)
4
Serial Port 3 (COM4)
IRQ4 via SERIRQ
Note (1)
5 N/A
N/A
Note
(1)
6 N/A
N/A
Note
(1)
7 N/A
N/A
Note
(1)
8 Real-time
clock
N/A
No
9
N/A
IRQ9 via SERIRQ
Note (1)
10
Serial Port 1 (COM1)
IRQ10 via SERIRQ
Note (1)
11
Serial Port 2 (COM2)
IRQ11 via SERIRQ
Note (1)
12
PS/2 Mouse
IRQ12 via SERIRQ
Note (1)
13
FERR# logic
N/A
Note (1)
14
SATA Primary
IRQ14 via SERIRQ
Note (1)
15
SATA Secondary
IRQ15 via SERIRQ
Note (1)
16 N/A
P.E.G Root Port, Intel HDA, PCIE Port
0/1/2/3/4/5/6, EHCI Conterller #2, I.G.D,
XHCI Controller
Note (1)
17
N/A
PCIE Port 0/1/2/3/4/5/6, P.E.G Root Port, Note (1)
18 N/A
PCIE Port 0/1/2/3/4/5/6, P.E.G Root Port,
SMBus Controller, EHCI Controller #2
Note (1)
19
N/A
PCIE Port 0/1/2/3/4/5/6, P.E.G Root Port, Note (1)
20 N/A
GbEController
Note
(1)
21 N/A
Note
(1)
22
N/A
Intel HDA
Note (1)
23
N/A
EHCI Controller #1
Note (1)
Note:
These IRQs can be used for PCI devices when onboard device is disabled.
Summary of Contents for nanoX-AL
Page 10: ...2 Introduction This page intentionally left blank...
Page 18: ...10 Specifications This page intentionally left blank...
Page 42: ...34 Smart Embedded Management Agent SEMA This page intentionally left blank...
Page 80: ...72 BIOS Setup This page intentionally left blank...
Page 90: ...82 BIOS Checkpoints Beep Codes This page intentionally left blank...