ADLINK Technology nanoX-AL User Manual Download Page 1

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Leading

EDGE COMPUTING

nanoX-AL

User’s Manual

COM Express Mini Size Type 10

Module with

Intel Atom®, Pentium®, Celeron® SoC

Manual Rev.:

1.3

Revision Date:

July 16, 2020

Part Number:

50-1J088-10

Summary of Contents for nanoX-AL

Page 1: ...Leading EDGE COMPUTING nanoX AL User s Manual COM Express Mini Size Type 10 Module with Intel Atom Pentium Celeron SoC Manual Rev 1 3 Revision Date July 16 2020 Part Number 50 1J088 1030...

Page 2: ...ucts manufacturing processes components and raw materials have as little impact on the environment as possible When products are at their end of life our customers are encouraged to dispose of them in...

Page 3: ...g 6 2 11 Power Specifications 6 2 12 Power Consumption 6 2 13 Operating Temperatures 6 2 14 Environmental 6 2 15 Specification Compliance 6 2 16 Operating Systems 7 2 17 Functional Diagram 8 2 18 Mech...

Page 4: ...28 4 4 MIPI60 Debug Header build option 29 4 5 Switch Settings 30 5 Smart Embedded Management Agent SEMA 31 5 1 Board Specific SEMA Functions 32 5 1 1 Voltages 32 5 1 2 Main Current 32 5 1 3 BMC Stat...

Page 5: ...Driver Health 56 7 3 14 Advanced Trusted Computing 56 7 3 15 Advanced Trusted Computing 57 7 4 Chipset 58 7 4 1 Chipset North Bridge 58 7 4 2 Chipset South Bridge 58 7 4 3 Chipset Uncore Configuratio...

Page 6: ...nformation 83 9 1 Board to Board Connectors 83 9 2 Thermal Solution 84 9 2 1 Heat Spreaders 84 9 2 2 Heat Sinks 84 9 2 3 Installation 84 9 3 Mounting Methods 86 9 4 Standoff Types 87 Safety Instructio...

Page 7: ...Diagram 8 Figure 2 nanoX AL Mechanical Drawing 9 Figure 3 nanoX AL Connector Switch and LED Locations 25 Figure 4 nanoX AL and the DB40 Debug Module 25 Figure 5 cExpress Switch Locations 30 Figure 6...

Page 8: ...ebug Connector Pin Definition 27 Table 3 nanoX AL LED Descriptions 28 Table 4 MIPI60 Debug Header Pin Definition 29 Table 5 BIOS Select and Mode Configuration Switch Settings 30 Table 6 SEMA Onboard V...

Page 9: ...JPEG MJPEG hardware decode Graphics outputs include DDI ports supporting HDMI DVI DisplayPort and single channel 18 24 bit LVDS eDP by build option The nanoX AL is specifically designed for customers...

Page 10: ...2 Introduction This page intentionally left blank...

Page 11: ...st Technology 2 0 Intel AES NI Intel TXT PCLMULQDQ instruction DRNG Notes Availability of features may vary between processor SKUs and operating systems N4200 M3350 by project basis L3 Cache 2MB for a...

Page 12: ...D Audio integrated on SoC Codec Located on carrier miniBASE 10R ALC262 standard support 2 5 LAN Intel MAC PHY Intel Ethernet Controller I210 Extreme Rugged operating temperature range Intel Ethernet C...

Page 13: ...ss Console Redirection Support COM 1 Supported by module SER0 A98 A99 via NCT5104D 10 0x240 Yes COM 2 Supported by module SER1 A101 A102 via NCT5104D 11 0x248 Yes COM 3 Supported by Super I O W83627DH...

Page 14: ...deep S5 for 5Vsb power saving 2 12 Power Consumption Please contact your ADLINK representative for the document COM Express Module Power Consumption 2 13 Operating Temperatures Standard Operating Tem...

Page 15: ...nanoX AL Specifications 7 2 16 Operating Systems Standard Support Windows 10 64 bit Linux 64 bit VxWorks 64 bit Extended Support BSP Linux 64 bit VxWorks 64 bit...

Page 16: ...b s port 0 1 8x USB 2 0 1 1 port 0 7 port 7 supports host and client mode MIPI60 60 pin PCIe x1 Gen2 eMMC 5 0 8 16 32GB build option LM73 4x GP0 4x GPI SDIO GP I2 C LPC Bus SPI SPI0 BIOS DDC I2 C SPI_...

Page 17: ...49 0 4 9 8 67 5 80 84 2 Top View Side View All are dimensions shown in millimeters Tolerances should be 0 25mm unless otherwise noted The tolerances of the module connector locating peg holes dimensi...

Page 18: ...10 Specifications This page intentionally left blank...

Page 19: ...5 LPC_AD1 ESPI_IO_1 6 GBE0_MDI2 6 LPC_AD2 ESPI_IO_2 7 GBE0_MDI2 7 LPC_AD3 ESPI_IO_3 8 GBE0_LINK 8 LPC_DRQ0 ESPI_ALERT0 9 GBE0_MDI1 9 LPC_DRQ1 ESPI_ALERT_1 10 GBE0_MDI1 10 LPC_CLK ESPI_CK 11 GND FIXED...

Page 20: ...1 55 RSVD 55 RSVD 56 RSVD 56 RSVD 57 GND 57 GPO2 58 PCIE_TX3 58 PCIE_RX3 59 PCIE_TX3 59 PCIE_RX3 60 GND FIXED 60 GND FIXED 61 PCIE_TX2 61 PCIE_RX2 62 PCIE_TX2 62 PCIE_RX2 63 GPI1 63 GPO3 64 PCIE_TX1 6...

Page 21: ...SPI_MOSI 95 DDI0_DDC_AUX_SEL 96 TPM_PP 96 USB7_HOST_PRSNT 97 TYPE10 97 SPI_CS 98 SER0_TX 98 DDI0_CTRLCLK_AUX 99 SER0_RX 99 DDI0_CTRLDATA_AUX 100 GND FIXED 100 GND FIXED 101 SER1_TX 101 FAN_PWMOUT 102...

Page 22: ...O 5V Output 5V signal level I O 3 3V Bi directional signal 3 3V tolerant I O 5V Bi directional signal 5V tolerant I O 3 3Vsb Input 3 3V tolerant active in standby state P Power Input Output REF Refere...

Page 23: ...0 eDP_TX2 LVDS_A0 eDP_TX2 LVDS_A1 eDP_TX1 LVDS_A1 eDP_TX1 LVDS_A2 eDP_TX0 LVDS_A2 eDP_TX0 LVDS_A3 LVDS_A3 A71 A72 A73 A74 A75 A76 A78 A79 LVDS Channel A differential pairs O LVDS LVDS_A_CK eDP_TX3 LVD...

Page 24: ...ects the function of DDI1_CTRLCLK_AUX and DDI1_CTRLDATA_AUX This pin shall have a 1M pull down to logic ground on the Module If this input is floating the AUX pair is used for the DP AUX signals If pu...

Page 25: ...pair O SATA AC coupled on Module SATA1_RX SATA1_RX B19 B20 Serial ATA channel 1 Receive Input differential pair I SATA AC coupled on Module S ATA_ACT A28 ATA parallel and serial or SAS activity indica...

Page 26: ...A45 USB differential data pairs for Port 0 I O 3 3VSB USB 1 1 2 0 compliant USB1 USB1 B46 B45 USB differential data pairs for Port 1 I O 3 3VSB USB 1 1 2 0 compliant USB2 USB2 A43 A42 USB differentia...

Page 27: ...arrier board may drive this line low I 3 3VSB PU 10k 3 3VSB Do not pull high on carrier USB0_HOST_PRSNT B48 Module USB client may detect the presence of a USB host on USB0 A high value indicates that...

Page 28: ...USB 2 0 PHY USB 3 0 PHY USB 3 0 2 0 Port 1 USB 2 0 PHY USB 3 0 PHY USB 2 0 Port 0 Host Device Mode PHY USB 2 0 USB 3 0 USB 2 0 USB 2 0 USB 2 0 USB 3 0 USB 2 0 USB 3 0 USB 2 0 USB 3 0 USB 2 0 USB 3 0...

Page 29: ...OS_DIS1 B88 Selection strap to determine the BIOS boot device I PU 10k 3 3VSB Carrier shall pull to GND or leave not connected 3 3 13 Miscellaneous Signal Pin Description I O PU PD Comment SPKR B32 Ou...

Page 30: ...data I O line I O OD 3 3VSB PU 2k2 3 3VSB Source SEMA BMC or Apollo Lake SoC as alternative BMC by default 3 3 16 General Purpose I O GPIO Signal Pin Description I O PU PD Comment GPO 0 A93 General p...

Page 31: ...PU 10k 3 3VSB CB_RESET B50 Reset output from module to Carrier Board Active low Issued by module chipset and may result from a low SYS_RESET input a low PWR_OK input a VCC_12V power input that falls...

Page 32: ...wer and Ground Signal Pin Description I O PU PD Comment VCC_12V A104 A109 B104 B109 Primary power input 12V nominal See section 7 Electrical Specifications for allowable input range All available VCC_...

Page 33: ...are not included in the PICMG standard specification 4 1 Connector Switch and LED Locations Figure 3 nanoX AL Connector Switch and LED Locations Note The optional MIPI60 Debug Header is located on th...

Page 34: ...to Jumper for Debug 5 For SMC Debug POSTWDT_DIS Connect to Jumper for Debug 6 SUS_S5 7 SUS_S4 8 SUS_S3 9 CB_PWROK 10 CB_RESET 11 SYS_RESET 12 Test Point PWRBTN 13 SMC_OCD0B Include a jumper to connect...

Page 35: ...power 3 3V provided from COM module 34 SPI_BIOS_CLK 35 SPI_BIOS_MOSI 36 SPI_BIOS_MISO 37 SPI_BIOS_CS1 38 SPI_BIOS_CS0 39 GND1 40 SPI Program Interface VCC_SPI_IN SPI Power Input from flash tool to mo...

Page 36: ...Power Source 3Vcc S0 LED ON S3 S4 S5 LED OFF ECO mode LED OFF LED3 Red BMC output and same signal as WDT B27 on BtB connector Module power up WD LED LED OFF Watchdog counting WD LED Keep Last State W...

Page 37: ..._DATA 1 21 PTI_0_DATA 1 22 PTI_1_DATA 2 23 PTI_0_DATA 2 24 PTI_1_DATA 3 25 PTI_0_DATA 3 26 No Connect 27 PTI_0_DATA 4 28 No Connect 29 PTI_0_DATA 5 30 No Connect 31 PTI_0_DATA 6 32 No Connect 33 PTI_0...

Page 38: ...e are configured as SPI1 Only one of the two is connected to the SPI bus at any given time In case of BIOS failure of the primary SPI1 BIOS the system will reboot and switch to the secondary SPI1 BIOS...

Page 39: ...re stored in flash Power cycles counter Boot counter Counts the number of boot attempts Watchdog Timer Set Reset Disable Watchdog Timer Features auto reload at power up System Restart Cause Power loss...

Page 40: ...e Main Current Function Table 6 SEMA Onboard Voltage Monitor 5 1 2 Main Current The BMC of the nanoX AL implements a current monitor The current can be read by calling the SEMA function Get Main Curre...

Page 41: ...rted Exception Code Error Message 0 NOERROR 2 NO_SUSCLK 3 NO_SLP_S5 4 NO_SLP_S4 5 NO_SLP_S3 6 NO_CB_PWRGD 7 BIOS_FAIL 8 RESET_FAIL 9 RESETIN_FAIL 10 CRITICAL_TEMP 11 POWER_FAIL 12 VOLTAGE_FAIL 13 NO_S...

Page 42: ...34 Smart Embedded Management Agent SEMA This page intentionally left blank...

Page 43: ...rupt 02Ch 02Dh P2SB ITSS interrupt 02Eh 02Fh P2SB LPC eSPI 030h 031h P2SB ITSS interrupt 034h 035h P2SB ITSS interrupt 038h 039h P2SB ITSS interrupt 03Ch 03Dh P2SB ITSS interrupt 040h P2SB ITSS Timer...

Page 44: ...Terminate 08Ch 08Eh P2SB LPC eSPI or PMC 08Fh P2SB Terminate 090h P2SB LPC eSPI 091h P2SB Terminate 092h P2SB ITSS CPU I F 093h P2SB Terminate 094h 096h P2SB LPC eSPI or PMC 097h P2SB Terminate 098h...

Page 45: ...upt Request IRQ Lines APIC Interrupt Map The following table describes the APIC interrupt mapping The Apollo Lake platform supports 120 IRQs in total IO APIC Pin Routing 0 8259 1 PS2 Keyboard 2 8254 C...

Page 46: ...urable sources including internal PIRQE SCI TCO internal ACPI PCI devices and HPET 21 Option for configurable sources including internal PIRQF SCI TCO internal ACPI PCI devices and HPET 22 Option for...

Page 47: ...N A IRQ9 via SERIRQ Note 1 10 Serial Port 1 COM1 IRQ10 via SERIRQ Note 1 11 Serial Port 2 COM2 IRQ11 via SERIRQ Note 1 12 PS 2 Mouse IRQ12 via SERIRQ Note 1 13 FERR logic N A Note 1 14 SATA Primary IR...

Page 48: ...SRAM 0 13 3 Audio 0 14 0 CSE HECI1 0 15 0 CSE HECI2 0 15 1 CSE HECI3 0 15 2 CSE fTPM PSF ghost 0 15 7 CSE HOFFL 0 16 0 ISH 0 17 0 SATA 0 18 0 PCIe A 1 0 19 0 PCIe A 2 0 19 1 PCIe A 3 0 19 2 PCIe B 1 m...

Page 49: ...31 1 6 5 PCI Interrupt Routing Map INT Line PCIE port1 PCIE port 2 PCIE port 3 PCIE Onboard LAN i210 Mobile IGFX PUNIT Device SMBus Controller Int0 INTA 22 INTB 23 INTC 22 INTB 21 NTD 19 Int1 INTB 23...

Page 50: ...33 Int3 INTD 30 INTD 34 INT Line SPI1 SPI3 SPI3 SD Host 0 SD Host 1 SD Host 2 SD Host 3 Int0 INTA 35 INTC 15 INTD 39 INTH 38 INTB 37 Int1 INTB 36 Int2 INTC 37 Int3 6 6 SMBus Address Table Device Addr...

Page 51: ...Save Exit BIOS Information System Information Board Information System Date and Time Access Level CPU Configuration Graphics Configuration Power Management System Management Thermal Management Watchd...

Page 52: ...BIOS Build Date MRC Version Info only Display MRC Version GOP Version Info only Display GOP Version TXE FW Version Info only Display TXE FW Version BIOS Boot Source Info only Display BIOS Boot Source...

Page 53: ...e Current Runtime Info only The returned value specifies the time in seconds the system is running in S0 state This counter is cleared when the system is removed from the external power supply Power C...

Page 54: ...lay cache info L1 Code Cache Info only Display cache info L2 Cache Info only Display cache info L3 Cache Inf o only Display cache info Speed Info only Display CPU Speed 64 bit Info only Display 64 bit...

Page 55: ...7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Power Limit 1 in Watts Auto will program Power Limit 1 based on silicon default support value Power Limit 1 Time Windows Auto 1 2 3 4 5 6 7 8 10...

Page 56: ...ffer overflow attacks can be prevented when combined with a supporting OS Thermal Monitor Disabled Enabled Enable Disable Thermal Monitor Monitor Mwait Disabled Enabled Auto Enable Disable Monitor Mwa...

Page 57: ...essage during system shutdown Lock Legacy Resources Disabled Enabled Enables or Disables Lock of Legacy Resources LID Function Disabled Enabled Enable Disable LID Function ECO Mode Disabled Enabled Re...

Page 58: ...SEMA Supported Features SEMA Supported Features Info only Display SEMA Supported Features Flags Submenu Flag Flags Info only BMC Flags Info Only BIOS Select Info Only ATX AT Mode Info Only Exception C...

Page 59: ...Smart Fan Temperature Source CPU Sensor Board Sensor CPU Smart Fan Temperature Source CPU Fan Mode AUTO Smart Fan Fan Off Fan On CPU Fan Mode PWM Level 0 100 Control PWM Level 7 3 6 Advanced Watchdog...

Page 60: ...ation NCT5104D Feature Options Description Serial Port 2 Configuration Submenu Set Parameters of Serial Port 2 COMB Serial Port 2 Configuration Info only Serial Port Disableed Enabled Enable or Disabl...

Page 61: ...Submenu The settings specify how the host computer and the remote computer which the user is using will exchange data Both computers should have the same or compatible settings The item will be lunch...

Page 62: ...s per second 9600 19200 38400 57600 115200 Selects serial port transmission speed The speed must be matched on the other side Long or noisy lines may require lower speeds Data Bits 7 8 Data Bits Parit...

Page 63: ...direction Settings Feature Options Description Legacy Serial Redirection Port COM1 COM2 COM3 COM4 Select a COM port to display redirection of Legacy OS and Legacy OPROM Messages 7 3 10 Advanced USB Fe...

Page 64: ...rt Smart Battery Function Disable Enable Enable Disable Battery Function 7 3 13 Advanced Driver Health Feature Options Description Driver Name Info only Provides Health Status for the Drivers Controll...

Page 65: ...3 TPM 20 Interface Type Info only Device Select TPM 1 2 TPM 2 0 Auto PM 1 2 will restrict support to TPM 1 2 devices TPM 2 0 will restrict support to TPM 2 0 devices Auto will support both with the d...

Page 66: ...VGA Workaround Disable Enable Enable it if your PCIe card cannot boot to DOS This is for Test only 7 4 2 Chipset South Bridge Feature Options Description Serial IRQ Mode Quiet Continuous Configure Se...

Page 67: ...electing the appropriate setup item GOP Brightness Level 20 40 60 80 100 120 140 160 180 200 220 240 255 Set GOP Brightness Level IGD Configuration Info only Integerated Graphics Devices Disable Enabl...

Page 68: ...uth Cluster Configuration PCI Express Configuration Feature Options Description PCI Express Configuration Info only PCIE Port assigned to LAN Info only Display PCIE Port assigned to LAN Information Co...

Page 69: ...sable Access Control Services Extended Capability URR Disable Enable CI Express Unsupported Request Reporting Enable Disable FER Disable Enable PCI Express Device Fatal Error Reporting Enable Disable...

Page 70: ...lection De0emphasis Disable Enable When the Link is operating at 5 0 GT s speed this bit selects the level of de emphasis for an Upstream component 1b 3 5 dB 0b 6 dB Chipset South Cluster Configuratio...

Page 71: ...dges behind this Root Bridge Reserved Memory 10 Reserved Memory and Prefetchable Memory 1 20MB Range for this Root Bridge Reserved I O 4 Reserved I O 4K 8K 12K 16K 20K Range for this Root Bridge PCH P...

Page 72: ...tal Error Reporting Enable Disable CER Disable Enable PCI Express Device Correctable Error Reporting Enable Disable CTO Default Setting 16 15 ms 65 210 ms 260 900 ms 1 3 5 s Disable PCI Express Comple...

Page 73: ...ation SATA Drives Feature Options Description SATA Drives Info only Chipset SATA Controller Configuration Info only Chipset SATA Disable Enable Enables or Disables the Chipset SATA Controller The Chip...

Page 74: ...e SATA Port SATA Port 1 Hot Plug Capability Disabled Enabled If enabled SATA port will be reported as Hot Plug capable Configured as eSATA Info only Display Configured as eSATA support Mechanical Pres...

Page 75: ...Description XHCI Pre Boot Driver Disabled Enabled Enable Disable XHCI Pre Boot Driver support XHCI Mode Disabled Enabled Once disabled XHCI controller would be function disabled none of the USB device...

Page 76: ...tion Info only State After G3 S0 State S5 State Last State Specify what state to go to when power is re applied after a power failure G3 state S0 State System will boot directly as soon as power appli...

Page 77: ...ssword Enter Password Set Setup Administrator Password User Password Enter Password Set User Password Secure Boot Submenu Customizable Secure Boot settings System Mode Info only Secure Boot Info only...

Page 78: ...ost during boot New Boot Option Policy Default Place First Place Last Controls the placement of newly detected UEFI boot option Boot mode select Legacy UEFI Select boot mode LEGACY UEFI 7 6 2 Boot FIX...

Page 79: ...scard Changes and Reset Reset system setup without saving any changes Save Options Info only Save Changes Save Changes done so far to any of the setup options Discard Change Discard Changes fone so fa...

Page 80: ...72 BIOS Setup This page intentionally left blank...

Page 81: ...y the Intel Platform Innovation Framework for EFI the Framework The Framework refers the following boot phases which may apply to various status code checkpoint descriptions Security SEC initial low l...

Page 82: ...overy errors PEI 8 2 Standard Status Codes 8 2 1 SEC Phase Status Code Description 0x00 Not used Progress Codes 0x01 Power on Reset type detection soft hard 0x02 AP initialization before microcode loa...

Page 83: ...Bridge initialization North Bridge module specific 0x19 Pre memory South Bridge initialization is started 0x1A Pre memory South Bridge initialization South Bridge module specific 0x1B Pre memory Sout...

Page 84: ...ge module specific 0x3F 0x4E OEM post memory initialization codes 0x4F DXE IPL is started PEI Error Codes 0x50 Memory initialization error Invalid memory type or incompatible memory speed 0x51 Memory...

Page 85: ...ess started 0xF3 Recovery firmware image is found 0xF4 Recovery firmware image is loaded 0xF5 0xF7 Reserved for future AMI progress codes Recovery Error Codes 0xF8 Recovery PPI is not available 0xF9 R...

Page 86: ...ecific 0x6E North Bridge DXE initialization North Bridge module specific 0x6F North Bridge DXE initialization North Bridge module specific 0x70 South Bridge DXE initialization is started 0x71 South Br...

Page 87: ...A3 IDE Enable 0xA4 SCSI initialization is started 0xA5 SCSI Reset 0xA6 SCSI Detect 0xA7 SCSI Enable 0xA8 Setup Verifying Password 0xA9 Start of Setup 0xAA Reserved for ASL see ASL Status Codes section...

Page 88: ...rror loading Boot Option LoadImage returned error 0xDA Boot Option is failed StartImage returned error 0xDB Flash update is failed 0xDC Reset protocol is not available 8 2 6 DXE Beep Codes of Beeps De...

Page 89: ...sitioned into ACPI mode Interrupt controller is in PIC mode 0xAA System has transitioned into ACPI mode Interrupt controller is in APIC mode 8 3 OEM Reserved Checkpoint Ranges Status Code Description...

Page 90: ...82 BIOS Checkpoints Beep Codes This page intentionally left blank...

Page 91: ...o board connector with 0 5mm for a stacking height of 5 mm This connector can be used with 5 mm through hole standoffs SMT type Tyco 3 6318491 6 Foxconn QT002206 4141 3H 220 pin board to board connect...

Page 92: ...is compatible with all COM Express modules 9 2 2 Heat Sinks A heat sink can be used as a thermal solution for a specific COM Express module and can have a fan or be fanless depending on the thermal r...

Page 93: ...AL Mechanical Information 85 Step 3 Put heatsink on the COM Express module and assemble the heatsink onto the COM Express module Use the four M2 5 L 6mm screws provided to fasten the heatsink to the m...

Page 94: ...ice of 5 mm or 8mm board to board connectors there is the choice of Top and Bottom mounting In Top mounting the threaded standoffs are on the carrier board and the thermal solution is equipped with th...

Page 95: ...andoffs are DIP type and through hole standoffs are SMT type Other types not listed are available upon request 5mm through hole standoff SMT type P N 33 72000 0050 5mm threaded standoff DIP type P N 3...

Page 96: ...To avoid electrical shock and or damage to equipment Keep equipment away from water or liquid sources Keep equipment away from high heat or high humidity Keep equipment properly ventilated do not bloc...

Page 97: ...08 360 0200 Toll Free 1 800 966 5200 USA only Fax 1 408 360 0222 Email info adlinktech com ADLINK Technology China Co Ltd Address 300 Fang Chun Rd Zhangjiang Hi Tech Park Pudong New Area Shanghai 2012...

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