ADLINK Technology LEC-BT, Technical Reference

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Interfaces 21
LEC-BT
3.19 Debug (DB40)
Table 3-4 lists the pin signals of the CN1 connector, which provides 40 pins, 1 row, consecutive
sequence with 0.02" (0.50mm) pitch.
P154 VDD_IN (Module power input voltage -
3.0V min to 5.25V max) S155 FORCE_RECOV# (Low on this pin allows
non-protected segments of Module boot
device to be rewritten / restored from an
external USB Host on Module USB0. The
Module USB0 operates in Client Mode when
the Force Recovery function is invoked.
Pulled high on the Module. For SOCs that
do not implement a USB based Force
Recovery function, then a low on the Module
FORCE_RECOV# pin
may invoke the SOC
native Force Recovery mode – such as over
a Serial Port. Pulled up on Module. Driven
by OD part on Carrier.)
P155 VDD_IN (Module power input voltage -
3.0V min to 5.25V max) S156 BATLOW# (Battery low indication to
Module. Carrier to float the line in inactive
state. Pulled up on Module. Driven by OD
part on Carrier.)
P156 VDD_IN (Module power input voltage -
3.0V min to 5.25V max) S157 TEST# (Held low by Carrier to invoke
Module vendor specific test function(s).
Pulled up on Module. Driven by OD part on
Carrier.)
S158 GND
Table 3-4: Debug Interface Signals (CN1)
Pin # Signal
1 RESVD
2 SMC_STATUS
3 BIOS_MODE
4 SEL_BIOS
5 POSTWDT_DIS#
6 SUS_S5#
7 SUS_S4#
8 SUS_S3#
9 CB_PWROK
10 CB_RESET#
11 SYS_RESET#
12 PWRBTN#
13 SMC_OCD0B
14 SMC_OCD0A
15 SMC_CLK
16 SMC_DATA
17 SMC_RESET_IN#
18 SMC_FLMD0
19 SMC_RXD6
20 SMC_TXD6
21 GND3
22 3V3_DUAL
Table 3-3: SMARC P-S Connector (GF1) Signal Descriptions (Continued)