ADLINK Technology LEC-BT, Technical Reference

Page: 23 / 46

Interfaces 17
LEC-BT
P71 USB2_EN_OC# (Pulled low by Module
OD driver to disable USB2 power. Pulled
low by Carrier OD driver to indicate over-
current situation. A pull-up
shall be
present on the Module to a 3.3V rail. The
pull-up rail
may be switched off to
conserve power if the USB port is not in
use. Further details may be found in
Section 4.12.4 of
SMARC Specification .)
S72 AFB_DIFF3- (maps to SATA_TX1_N on the
SOC)
P72 PCIE_C_PRSNT# (PCIe Port C present
input. Pulled up or terminated on Module) S73 GND
P73 PCIE_B_PRSNT# (PCIe Port B present
input. Pulled up or terminated on Module) S74 AF (maps to SATA_RX1_P on the
SOC)
P74 PCIE_A_PRSNT# (PCIe Port A present
input. Pulled up or terminated on Module) S75 AFB_DIFF4- (maps to SATA_RX1_N on the
SOC)
Key Key
P75 PCIE_A_RST# (PCIe Port A reset output) S76 PCIE_B_RST# (PCIe Port B reset output,
active low)
P76 PCIE_C_CKREQ# (PCIe Port C clock
request input. Pulled up or terminated on
Module) S77 PCIE_C_RST# (PCIe Port A reset output,
active low)
P77 PCIE_B_CKREQ# (PCIe Port B clock
request input. Pulled up or terminated on
Module) S78 PC (Differential PCIe Link C
receive data pair 0. No coupling caps on
Module)
P78 PCIE_A_CKREQ# (PCIe Port A clock
request input. Pulled up or terminated on
Module) S79 PCIE_C_RX- (Differential PCIe Link C
receive data pair 0. No coupling caps on
Module)
P79 GND S80 GND
P80 PCIE_ (Differential PCIe Link
C reference clock output. DC coupled) S81 PC (Differential PCIe Link C
transmit data pair 0. Series coupling caps
are on the Module. Caps are 0402 package
0.1uF)
P81 PCIE_C_REFCK- (Differential PCIe Link
C reference clock output. DC coupled) S82 PCIE_C_TX- (Differential PCIe Link C
transmit data pair 0. Series coupling caps
are on the Module. Caps are 0402 package
0.1uF)
P82 GND S83 GND
P83 PCIE_ (Differential PCIe Link
A reference clock output. DC coupled) S84 PCIE_ (Differential PCIe Link B
reference clock output; DC coupled)
P84 PCIE_A_REFCK- (Differential PCIe Link
A reference clock output. DC coupled) S85 PCIE_B_REFCK- (Differential PCIe Link B
reference clock output; DC coupled)
P85 GND S86 GND
P86 PC (Differential PCIe Link A
receive data pair 0. No coupling caps on
Module) S87 PC (Differential PCIe Link B
receive data pair 0. No coupling caps on
Module)
P87 PCIE_A_RX- (Differential PCIe Link A
receive data pair 0. No coupling caps on
Module) S88 PCIE_B_RX- (Differential PCIe Link B
receive data pair 0. No coupling caps on
Module)
P88 GND S89 GND
P89 PC (Differential PCIe Link A
transmit data pair 0. Series coupling
capacitors are on the Module. 0.1 uF 0402
capacitor are on module) S90 PC (Differential PCIe Link B
transmit data pair 0. Series coupling caps
are on the Module Caps are 0402 package
0.1uF)
Table 3-3: SMARC P-S Connector (GF1) Signal Descriptions (Continued)