ADLINK Technology intel COM Express Express-TL User Manual Download Page 43

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Express-TL User’s Guide

PICMG COM.0 R3.0

Page 43

4.4.2

PCI Express

Name

Pin #

Description

I/O

PU / PD Comment

PCIE_TX6-

D19

D20

PCI Express channel 6, Transmit Output differential pair.

O PCIE

AC coupled on Module

PCIE_RX6-

C19

C20

PCI Express channel 6, Receive Input differential pair.

I PCIE

AC coupled off Module

PCIE_TX7-

D22

D23

PCI Express channel 7, Transmit Output differential pair.

O PCIE

AC coupled on Module

PCIE_RX7-

C22

C23

PCI Express channel 7, Receive Input differential pair.

I PCIE

AC coupled off Module

4.4.2.1.

PCH HSIO Lane Assignments

Refer to Section 4.3.6.1 PCH HSIO Lane Assignments on page 33.

Summary of Contents for intel COM Express Express-TL

Page 2: ...e PICMG COM 0 R3 0 Page 2 Copyright 2022 ADLINK Technology Inc Revision History Revision Description Date Author 1 0 Initial release 2021 12 16 JC 1 1 Update pin definitions update I O and LED specifi...

Page 3: ...ctrical and Electronic Equipment WEEE directive Environmental protection is a top priority for ADLINK We have enforced measures to ensure that our products manufacturing processes components and raw m...

Page 4: ...s cables when installing mounting or un installing removing equipment To avoid electrical shock and or damage to equipment Keep equipment away from water or liquid sources Keep equipment away from hig...

Page 5: ...noting special levels of information Note This information adds clarity or specifics to text and illustrations Caution This information indicates the possibility of minor physical injury component dam...

Page 6: ...CA 95119 1208 USA Tel 1 408 360 0200 Toll Free 1 800 966 5200 USA only Fax 1 408 600 1189 Email info adlinktech com ADLINK Technology China Co Ltd 300 Fang Chun Rd Zhangjiang Hi Tech Park Pudong New A...

Page 7: ...i I O and Storage 14 2 7 Trusted Platform Module TPM 15 2 8 SEMA Board controller 15 2 9 Debug 16 2 10 Power 16 2 11 Mechanical and Environmental 16 3 Block Diagram 18 4 Pinout and Signal Descriptions...

Page 8: ...e Definition 56 4 4 8 Power and Ground 57 5 Additional Features 58 5 1 Module Feature Locations 58 5 2 Debug Connector 60 5 3 Status LEDs 61 5 4 Exception Codes 62 5 5 Fan Connector 63 5 6 BIOS Defaul...

Page 9: ...Module rear side row and pin numbering 19 Figure 3 Module feature locations top side 58 Figure 4 Module feature locations bottom side 59 Figure 5 Express TL and Debug Module 60 Figure 6 Module mechani...

Page 10: ...tion DXVA support for full H 265 HEVC 10 bit VP9 hardware codecs In addition High Dynamic Range is supported for enhanced picture color and quality and digital content protection has been upgraded to...

Page 11: ...3 1 GHz 8MB 25W 4C 8T Intel Core i3 11100HE 2 4 4 4 GHz 8MB 45W 35W cTDP 4C 8T Intel Celeron 6600HE 2 6GHz 8MB 35W 2C 2T Supporting Intel VT Intel VT d Intel TXT Intel SSE4 2 Intel HT Technology Intel...

Page 12: ...ture Support 4 independent and simultaneous combinations of DisplayPort HDMI LVDS graphics outputs 4x 4K 60Hz eDP optional in place of LVDS VGA optional in place of DDI 3 Encode transcode HD content P...

Page 13: ...l Display Ports DDI support DisplayPort 1 4a HDMI 2 0b or DVI VGA VGA BOM option support in place of DDI 3 max resolution 1920x1200 60Hz Note USB4 is a build option HW and BIOS supported by project ba...

Page 14: ...5 V Intel Xeon processor pairs with I225 IT by default other combinations supported by project basis 2 6 Multi I O and Storage USB 4x USB 3 2 Gen2 USB 0 1 2 3 4x USB 2 0 1 1 USB 4 5 6 7 SuperSpeedPlus...

Page 15: ...scription IRQ Address Console Redirection Support COM 1 Supported by module SER0 A98 A99 via embedded controller 4 0x3F8 Yes COM 2 Supported by module SER1 A101 A102 via embedded controller 3 0x2F8 Ye...

Page 16: ...0 compliant Smart Battery support Power States C1 C6 S0 S1 S3 S4 S5 S5 ECO mode Wake on USB S3 S4 WoL S3 S4 S5 ECO Mode support for deep S5 for 5Vsb power saving Power Consumption Please contact your...

Page 17: ...yright 2022 ADLINK Technology Inc Shock and Vibration IEC 60068 2 64 and IEC 60068 2 27 MIL STD 202F Method 213B Table 213 I Condition A and Method 214A Table 214 I Condition D HALT tested Thermal Str...

Page 18: ...Gen Intel Core Celeron Processor Tiger Lake H DDI B eDP 4lanes eSPI 2 MIPI CSI 1 PCIe Gen4 x4 TCP 0 Mobile Intel Next Series Chipset RM590E QM580E HM570E SATA 6Gb s 1 PCIe Gen3 USB 3 2 Gen2 x1 USB 3...

Page 19: ...ble list of all signal pins supported on the dual 220 pin COM Express connectors as defined for Type 6 in the PICMG COM 0 R3 0 specification Signals described in the specification but not supported on...

Page 20: ...R6 D15 DDI1_CTRLCLK_AUX A16 SATA0_TX B16 SATA1_TX C16 DDI1_PAIR6 D16 DDI1_CTRLDATA_AUX A17 SATA0_TX B17 SATA1_TX C17 RSVD D17 RSVD A18 SUS_S4 B18 SUS_STAT ESPI_RESET C18 RSVD D18 RSVD A19 SATA0_RX B19...

Page 21: ...C_SERIRQ ESPI_CS1 B50 CB_RESET C50 DDI3_PAIR3 D50 DDI2_PAIR3 A51 GND FIXED B51 GND FIXED C51 GND FIXED D51 GND FIXED A52 PCIE_TX5 B52 PCIE_RX5 C52 PEG_RX0 D52 PEG_TX0 A53 PCIE_TX5 B53 PCIE_RX5 C53 PEG...

Page 22: ...84 GND D84 GND A85 GPI3 B85 VCC_5V_SBY C85 PEG_RX10 D85 PEG_TX10 A86 RSVD B86 VCC_5V_SBY C86 PEG_RX10 D86 PEG_TX10 A87 eDP_HPD B87 VCC_5V_SBY C87 GND D87 GND A88 PCIE0_CK_REF B88 BIOS_DIS1 C88 PEG_RX1...

Page 23: ...2V A110 GND FIXED B110 GND FIXED C110 GND FIXED D110 GND FIXED Note Strike through entries are not supported functions on this product eDP in place of LVDS and VGA in place of DDI 3 are BOM option sup...

Page 24: ...3V tolerant I O 5V Bi directional signal 5V tolerant I O 3 3VSB Input or output 3 3V tolerant active in standby state DDC Display Data Channel PCIE PCI Express compatible differential signal PEG PCI E...

Page 25: ...3VSB AC_SYNC HDA_SYNC A29 Sample synchronization signal to the CODEC s O 3 3VSB PCH internal PD 20Kohm AC_BITCLK HDA_BITCLK A32 Serial data clock generated by the external CODEC s I O 3 3VSB AC_SDOUT...

Page 26: ...drive a 37 5 Ohm equivalent load O Analog PD 150R VGA_BLU B92 Blue for monitor Analog DAC output designed to drive a 37 5 Ohm equivalent load O Analog PD 150R VGA_HSYNC B93 Horizontal sync output to...

Page 27: ...low Pin LVDS mode eDP mode A71 A72 LVDS_A0 LVDS_A0 eDP_TX2 eDP_TX2 A73 A74 LVDS_A1 LVDS_A1 eDP_TX1 eDP_TX1 A75 A76 LVDS_A2 LVDS_A2 eDP_TX0 eDP_TX0 A78 A79 LVDS_A3 LVDS_A3 A81 A82 LVDS_A_CK LVDS_A_CK e...

Page 28: ...LVDS_B0 LVDS_B0 LVDS_B1 LVDS_B1 LVDS_B2 LVDS_B2 LVDS_B3 LVDS_B3 B71 B72 B73 B74 B75 B76 B77 B78 LVDS Channel B differential pairs O LVDS LVDS_B_CK LVDS_B_CK B81 B82 LVDS Channel B differential clock O...

Page 29: ...fferential pairs O PCIE AC coupled off module eDP_VDD_EN A77 eDP power enable O 3 3V PD 100K eDP_BKLT_EN B79 eDP backlight enable O 3 3V PD 100K eDP_BKLT_CTRL B83 eDP backlight brightness control O 3...

Page 30: ...0 A5 Gigabit Ethernet Controller 0 1000Mbit sec link indicator active low OD 3 3VSB GBE0_CTREF A14 Reference voltage for Carrier Board Ethernet channel 1 and 2 magnetics center tap The reference volta...

Page 31: ...nput differential pair I SATA AC coupled on Module SATA2_TX SATA2_TX A22 A23 Serial ATA channel 2 Transmit Output differential pair O SATA AC coupled on Module SATA2_RX SATA2_RX A25 A26 Serial ATA cha...

Page 32: ...CIE_RX2 PCIE_RX2 B61 B62 PCI Express channel 2 Receive Input differential pair I PCIE AC coupled off Module PCIE_TX3 PCIE_TX3 A58 A59 PCI Express channel 3 Transmit Output differential pair O PCIE AC...

Page 33: ...OM 0 R3 0 Page 33 Copyright 2022 ADLINK Technology Inc 4 3 6 1 PCH HSIO Lane Assignments Name HSIO name on SOC Comment PCIE0 HSIO 22 PCIE1 HSIO 23 PCIE2 HSIO 24 PCIE3 HSIO 25 PCIE4 HSIO 30 PCIE5 HSIO...

Page 34: ...xed address command and data bus I O 3 3VSB LPC_FRAME B3 LPC frame indicates the start of an LPC cycle O 3 3VSB LPC_DRQ0 LPC_DRQ1 B8 B9 LPC serial DMA request I 3 3V Not connected LPC_SERIRQ A50 LPC s...

Page 35: ...ta pairs for Port 5 I O 3 3VSB USB 1 1 2 0 compliant USB7 USB7 B37 B37 USB differential data pairs for Port 6 I O 3 3VSB USB 1 1 2 0 compliant USB_0_1_OC B44 USB over current sense USB ports 0 and 1 s...

Page 36: ...A94 Clock from module to carrier board SPI BIOS flash O 3 3VSB SPI_POWER A91 Power supply for Carrier Board SPI sourced from Module nominally 3 3V The Module shall provide a minimum of 100mA on SPI_PO...

Page 37: ...RIP A35 Active low output indicating that the CPU has entered thermal shutdown O 3 3VSB PU 100K 3 3VSB FAN_PWMOUT B101 Fan speed control Uses the Pulse Width Modulation PWM technique to control the fa...

Page 38: ...main power rails I O OD 3 3VSB PU 2 2K 3 3VSB SMB_ALERT B15 System Management Bus Alert active low input can be used to generate an SMI System Management Interrupt or to wake the system Power sourced...

Page 39: ...eneral purpose input pins Pulled high internally on the module I 3 3V PU 10K 3 3V GPI 2 A67 General purpose input pins Pulled high internally on the module I 3 3V PU 10K 3 3V GPI 3 A85 General purpose...

Page 40: ...peration used to notify LPC devices O 3 3VSB SUS_S3 A15 Indicates system is in Suspend to RAM state Active low output An inverted copy of SUS_S3 on the carrier board also known as PS_ON may be used to...

Page 41: ...used P 8 5 20 V VCC_5V_SBY B84 B85 B86 B87 Standby power input 5 0V nominal If VCC5_SBY is used all available VCC_5V_SBY pins on the connector s shall be used Only used for standby and suspend functio...

Page 42: ...module USB_SSTX1 USB_SSTX1 D6 D7 Additional Transmit signal differential pairs for the SuperSpeed USB data path on USB1 O PCIE AC coupled on module USB_SSRX2 USB_SSRX2 C9 C10 Additional Receive signal...

Page 43: ...pled on Module PCIE_RX6 PCIE_RX6 C19 C20 PCI Express channel 6 Receive Input differential pair I PCIE AC coupled off Module PCIE_TX7 PCIE_TX7 D22 D23 PCI Express channel 7 Transmit Output differential...

Page 44: ...AIR5 DDI1_PAIR5 C29 C30 DDI1_PAIR6 DDI1_PAIR6 C15 C16 DDI1_HPD C24 DP1_HPD HDMI1_HPD DDI1_CTRLCLK_AUX D15 DP1_AUX HMDI1_CTRLCLK DDI1_CTRLCLK_AUX D16 DP1_AUX HMDI1_CTRLDATA DDI1_DDC_AUX_SEL D34 DDI1_DD...

Page 45: ...plug and notification of the link layer I 3 3V PD 100K Module must tolerate high level in stand by mode The carrier board shall include a blocking FET on DP1_HPD to prevent back drive current from dam...

Page 46: ...rs shall be placed on the Carrier TMDS1_CLK TMDS1_CLK D36 D37 HDMI Port Differential Pair Clock Lines HDMI_HPD C24 Detection of Hot Plug Unplug and notification of the link layer I 3 3V PD 100K HDMI1_...

Page 47: ...MDS2_CLK DDI2_HPD D44 DP2_HPD HDMI2_HPD DDI2_CTRLCLK_AUX C32 DP2_AUX HMDI2_CTRLCLK DDI2_CTRLCLK_AUX C33 DP2_AUX HMDI2_CTRLDATA DDI2_DDC_AUX_SEL C34 DDI2_DDC_AUX_SEL DDI2_DDC_AUX_SEL Note Dual Mode HDM...

Page 48: ...plug and notification of the link layer I 3 3V PD 100K Module must tolerate high level in stand by mode The carrier board shall include a blocking FET on DP1_HPD to prevent back drive current from dam...

Page 49: ...s shall be placed on the Carrier TMDS2_CLK TMDS2_CLK D49 D50 HDMI Port Differential Pair Clock Lines HDM2_HPD D44 Detection of Hot Plug Unplug and notification of the link layer I 3 3V PD 100K HDMI2_C...

Page 50: ...MDS3_CLK DDI3_HPD C44 DP3_HPD HDMI3_HPD DDI3_CTRLCLK_AUX C36 DP3_AUX HMDI3_CTRLCLK DDI3_CTRLCLK_AUX C37 DP3_AUX HMDI3_CTRLDATA DDI3_DDC_AUX_SEL C38 DDI3_DDC_AUX_SEL DDI3_DDC_AUX_SEL Note Dual Mode HDM...

Page 51: ...plug and notification of the link layer I 3 3V PD 100K Module must tolerate high level in stand by mode The carrier board shall include a blocking FET on DP1_HPD to prevent back drive current from dam...

Page 52: ...rs shall be placed on the Carrier TMDS3_CLK TMDS3_CLK C49 C50 HDMI Port Differential Pair Clock Lines HDM3_HPD C44 Detection of Hot Plug Unplug and notification of the link layer I 3 3V PD 100K HDMI3_...

Page 53: ...e the same lines as PCIE_TX 16 31 and in Module pin out Type 6 O PCIE AC coupled on Module PEG_RX2 PEG_RX2 C58 C59 PCI Express Graphics receive differential pairs These are the same lines as PCIE_TX 1...

Page 54: ...as PCIE_TX 16 31 and in Module pin out Type 6 I PCIE AC coupled off Module PEG_TX8 PEG_TX8 D78 D79 PCI Express Graphics transmit differential pairs These are the same lines as PCIE_TX 16 31 and in Mod...

Page 55: ...These are the same lines as PCIE_TX 16 31 and in Module pin out Type 6 O PCIE AC coupled on Module PEG_RX13 PEG_RX13 C94 C95 PCI Express Graphics receive differential pairs These are the same lines a...

Page 56: ...present X TYPE2 TYPE1 TYPE0 X X X Pinout Type 1 X X X Pinout Type 10 NC NC NC Pinout Type 2 NC NC GND Pinout Type 3 NC GND NC Pinout Type 4 NC GND GND Pinout Type 5 GND NC NC Pinout Type 6 GND NC GND...

Page 57: ...105 D106 D107 D108 D109 Primary power input supports wide range 5 20V input All available VCC_12V pins on the connector s shall be used P 8 5 20 V GND C1 C2 C5 C8 C11 C14 C21 C31 C41 C51 C60 C70 C73 C...

Page 58: ...describes connectors LEDs switches and additional items located on the module and not necessarily included in the PICMG standard spec ification The locations of these items are as below 5 1 Module Fea...

Page 59: ...Express TL User s Guide PICMG COM 0 R3 0 Page 59 Copyright 2022 ADLINK Technology Inc Figure 4 Module feature locations bottom side 30 pin Debug Connector PCI Express Configuration Switch...

Page 60: ...carrier design and bring up phase It offers access to the following critical parts of the module Test points measurement of internal power rails SPI BIOS programming interface Embedded Controller pro...

Page 61: ...Codes below LED2 Green Power Source 3Vcc S0 LED ON S3 S4 S5 LED OFF ECO mode LED OFF LED3 Red BMC output and same signal as WDT B27 on BtB connector Module power up WD LED LED OFF Watchdog counting W...

Page 62: ...ology Inc 5 4 Exception Codes Exception Code Error Message 0 NOERROR 3 NO_SLP_S5 4 NO_SLP_S4 5 NO_SLP_S3 6 BIOS_FAIL 7 RESET_FAIL 9 NO_CB_PWROK 10 CRITICAL_TEMP 11 POWER_FAIL 12 VOLTAGE_FAIL 13 RSMRST...

Page 63: ...Express TL User s Guide PICMG COM 0 R3 0 Page 63 Copyright 2022 ADLINK Technology Inc 5 5 Fan Connector Connector type JVE 24W1125A 04M00 Name Description 1 FAN_PWMOUT 2 FAN_TACHIN 3 GND 4 12V 4 3 2 1...

Page 64: ...t of BIOS default settings perform the following steps 1 Shut down the system 2 Keep the BIOS Setup Defaults Reset Button pressed and boot up the system You can release the button when the BIOS prompt...

Page 65: ...5 7 PCI Express Configuration Switch The PCI Express Configuration Switch allows you to configure the PCI Express x16 lanes from the CPU as 1 PCIe x16 2 PCIe x8 or 1 PCIe x8 2 PCIe x4 Mode Pin 1 Pin 2...

Page 66: ...in the SPI0 slot on the carrier In dual BIOS Failsafe mode both BIOS chips on the module are configured as SPI1 Only one of the two is connected to the SPI bus at any given time In case of failure of...

Page 67: ...e task the system is currently executing Checkpoints are very useful in aiding software developers or technicians in debugging problems that occur during the pre boot process on production hardware A...

Page 68: ...Page 68 Copyright 2022 ADLINK Technology Inc 7 Software Support 7 1 Windows 10 IoT Enterprise 64 bit 7 2 Yocto Linux 64 bit https github com ADLINK meta adlink x86 64bit TBC 7 3 Ubuntu Under planning...

Page 69: ...ttom View 0 4 80 121 125 72 68 50 24 0 4 91 90 73 26 56 95 91 4 Top View 2 9 25 0 25 8 05 0 25 Front View 8 Mechanical and Thermal 8 1 Module Dimensions Figure 6 Module mechanical dimensions All dimen...

Page 70: ...ss TL User s Guide PICMG COM 0 R3 0 Page 70 Copyright 2022 ADLINK Technology Inc 95 95 76 65 87 11 5 M2 5 4pcs M2 5 2pcs 8 2 Thermal Solutions 8 2 1 Heatspreader HTS Figure 7 Heatspreader HTS Dimensio...

Page 72: ...ess TL User s Guide PICMG COM 0 R3 0 Page 72 Copyright 2022 ADLINK Technology Inc 25 1 95 95 76 87 5 M2 5 4pcs M2 5 2pcs 8 2 3 Heatsink High Profile THSH Figure 9 Heatsink High Profile THSH Dimensions...

Page 73: ...xpress TL User s Guide PICMG COM 0 R3 0 Page 73 Copyright 2022 ADLINK Technology Inc 39 4 5 95 95 76 87 M2 5 x4pcs M2 5 2pcs 8 2 4 Heatsink with Fan THSF Figure 10 Heatsink with Fan THSF Dimensions mm...

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