ADLINK Technology ETX-BT User Manual Download

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ETX-BT

Revision History

Revision Description

Date

1.00 Initial

release

2015-03-18

1.01

Correct SPI Boot Device Switch settings

2015-05-07 JC

1.02

Correct SPI Boot Device settings; SPI0 fail-safe as default

2015-06-12 JC

1.03

Correct LPC-to-ISA bridge in block diagram

2015-12-16 JC

1.10

Updated for PATA to SATA version; BIOS chapter updated 2017-02-06 JC

1.2

Updated functional diagram, specifications, signal
descriptions, BIOS

2018-01-15 JC

1.3

Update memory support from 4GB to 8GB

2019-0

-0

Summary of Contents for ETX-BT

Page 1: ...Leading EDGE COMPUTING ETX BT User s Manual PATA to SATA version Manual Revision 1 3 Revision Date July 3 2019 Part Number 50 1J059 1060...

Page 2: ...al and Electronic Equipment WEEE directive Environmental protection is a top priority for ADLINK We have enforced measures to ensure that our products manufacturing processes components and raw materi...

Page 3: ...02 Correct SPI Boot Device settings SPI0 fail safe as default 2015 06 12 JC 1 03 Correct LPC to ISA bridge in block diagram 2015 12 16 JC 1 10 Updated for PATA to SATA version BIOS chapter updated 201...

Page 4: ...ons 13 5 Pinouts and Signal Descriptions 14 5 1 X1 PCI Bus USB Audio 14 5 2 X2 ISA 17 5 3 X3 LVDS Serial Parallel KB MS 20 5 4 X4 IDE 1 IDE 2 Ethernet Miscellaneous 23 6 Module Interfaces 26 6 1 Conne...

Page 5: ...ap 42 8 2 I O Map 42 8 3 Interrupt Request IRQ Lines 43 8 4 PCI Configuration Space Map 45 8 5 PCI Interrupt Routing Map 46 8 6 SMBus Address Table 47 8 7 I2 C Address Table 47 9 BIOS Setup 48 9 1 Men...

Page 6: ...ture are also available The module supports a single SODIMM for up to 8GB of DDR3L system memory and comes with integrated support for high resolution VGA and single dual channel LVDS Optionally a thi...

Page 7: ...el SSE4 1 and SSE4 2 Intel 64 architecture IA 32 bit PCLMULQDQ Instruction DRNG Intel Thermal Monitor TM1 TM2 Note Availability of features may vary between processor SKUs X Memory Single SODIMM socke...

Page 8: ...flops 4x anti aliasing o Full HW acceleration for decode of H 264 MPEG2 MVC VC 1 VP8 MJPEG o Full HW acceleration for encode of H 264 MPEG2 MVC o Supports 2 0 Stereoscopic 3D Stretch and Polyphase 8 t...

Page 9: ...Following modes are examples of what can be supported Note Except for defaults these are build options that require special part numbers Port Function 1 PATA default PATA SATA SATA 2 SATA default PATA...

Page 10: ...t monitor ECO mode support o Flat Panel Control Additional DDC I2C bus control for PWM control on carrier LVDS brightness PWM output switchable by BIOS with GPU PWM output Vdde inhibit Backlight Enabl...

Page 11: ...onal X Humidity 5 90 RH operating non condensing 5 95 RH storage operating with conformal coating X Shock and Vibration IEC 60068 2 64 and IEC 60068 2 27 MIL STD 202F Method 213B Table 213 I Condition...

Page 12: ...0 1 1 PCIe PCIe PCIe to PCI XIO2001 TPM Atmel AT97SC3204 X2 X1 Codec ALC262 LPC to ISA F85226AF SATA to PATA 2 Master only SEMA SMC i2C SMBus LM73 SPI 0 BIOS SPI 1 BIOS Super IO Nuvoton W83627DHG PT...

Page 13: ...ETX BT 13 4 Mechanical Dimensions Top View Side View All tolerances 0 05 mm Other tolerances 0 2 mm...

Page 14: ...10 GNT3 59 LOCK 60 DEVSEL 11 GNT2 12 3V 61 TRDY 62 USB3 13 REQ2 14 GNT1 63 IRDY 64 STOP 15 REQ1 16 3V 65 FRAME 66 USB2 17 GNT0 18 RESERVED 67 GND 68 GND 19 VCC 20 VCC 69 AD16 70 CBE2 21 SERIRQ 22 REQ...

Page 15: ...us Request 0 I 3 3 PU 8k2 3 3V 23 AD0 PCI Address Data Bus line IO 3 3 24 3V Power 3 3V PWR 25 AD1 PCI Address Data Bus line IO 3 3 26 AD2 PCI Address Data Bus line IO 3 3 27 AD4 PCI Address Data Bus...

Page 16: ...USB3P USB Data Port3 I O DP 73 AD19 PCI Address Data Bus line IO 3 3 74 AD18 PCI Address Data Bus line IO 3 3 75 AD20 PCI Address Data Bus line IO 3 3 76 USB0N USB Data Port0 I O DP 77 AD22 PCI Addres...

Page 17: ...DACK5 67 GND 68 GND 19 MEMR 20 DREQ0 69 SA13 70 DREQ3 21 LA17 22 DACK0 71 SA14 72 DACK3 23 LA18 24 IRQ14 73 SA15 74 IOR 25 LA19 26 IRQ15 75 SA16 76 IOW 27 LA20 28 IRQ12 77 SA18 78 SA17 29 LA21 30 IRQ1...

Page 18: ...4k7 5V int PU 100k 24 IRQ14 ISA Interrupt Request 14 ROMChip Select IO PU 4k7 5V 25 LA19 ISA Address Bus SA19 O PU 4k7 5V int PU 100k 26 IRQ15 ISA Interrupt Request 15 IO PU 4k7 5V 27 LA20 ISA Addres...

Page 19: ...ess Bus O PU 4k7 5V int PU 100k 74 IOR ISA I O Read IO PU 8k2 5V int PU 100k 75 SA16 ISA Address Bus O PU 4k7 5V int PU 100k 76 IOW ISA I O Write IO PU 8k2 5V int PU 100k 77 SA18 ISA Address Bus O PU...

Page 20: ...5 67 RTS2 68 PD5 19 LCDDO12 20 LCDDO14 69 DTR2 70 SLIN 21 GND 22 GND 71 DCD2 72 PD4 23 LCDDO8 24 LCDDO11 73 DSR2 74 PD3 25 LCDDO9 26 LCDDO10 75 CTS2 76 PD2 27 GND 28 GND 77 TXD2 78 PD1 29 LCDDO4 30 LC...

Page 21: ...1 O DP 20 LCD14 Second LVDS Ch Data Txout 2 O DP 21 GND Ground PWR 22 GND Ground PWR 23 LCD8 First LVDS Ch Data Txout 3 O DP 24 LCD11 Second LVDS Ch Data Txout 0 O DP 25 LCD9 First LVDS Ch Data Txout...

Page 22: ...et Ready COM2 I 5 74 PD3 RDATA LPT Data Bus D3 IO 5 75 CTS2 Clear to Send COM2 I 5 76 PD2 WP LPT Data Bus D2 IO 5 77 TXD2 Data Transmit COM2 O 3 3 PU 1k 3 3V 78 PD1 TRK0 LPT Data Bus D1 IO 5 79 RI2 Ri...

Page 23: ...SMBCLK 24 SMBDATA 73 SIDE_D11 74 PIDE_D3 25 SIDE_CS3 26 SMBALRT 75 SIDE_D4 76 PIDE_D11 27 SIDE_CS1 28 DASP_S 77 SIDE_D10 78 PIDE_D4 29 SIDE_A2 30 PIDE_CS3 79 SIDE_D5 80 PIDE_D10 31 SIDE_A0 32 PIDE_CS...

Page 24: ...k2 3 3VSB 24 SMBDATA SM Bus Data IO 3 3 PU 2k2 3 3VSB 25 S_CS3 Secondary IDE Chip Select Channel 1 O 3 3 26 SMBALERT SM Bus Alert I 3 3 PU 10k 3 3VSB 27 S_CS1 Secondary IDE Chip Select Channel 0 O 3 3...

Page 25: ...IDE Data Bus IO 73 S_D11 Secondary IDE Data Bus IO 74 P_D3 Primary IDE Data Bus IO 75 S_D4 Secondary IDE Data Bus IO 76 P_D11 Primary IDE Data Bus IO 77 S_D10 Secondary IDE Data Bus IO 78 P_D4 Primary...

Page 26: ...outs LEDs and switches that are used on the module but which interfaces are not part of the ETX standard specification 6 1 Connector Switch and LED Locations Component Side GbE Fan Reset BIOS CMOS SW2...

Page 27: ...ETX BT 27 Solder Side PCI Voltage Selection SW3 SPI Boot Selection SW1...

Page 28: ...V provide from COM module 13 BMC Program interface cont d OCD0B Include a jumper to connect OCD0A via 1K0 pull up to 3 3V_BMC 32 GND 12 PWRBTN 31 BIOS_DIS0 11 SYS_RESET 30 RST 10 CB_RESET 29 CLK33_LP...

Page 29: ...er Changes RESET see Section 7 1 Exception Codes LED2 Green Power Source 3Vcc S0 LED ON S3 S4 S5 LED OFF ECO mode LED OFF LED3 Red BMC output and same signal as WDT B27 on BtB connector Module power u...

Page 30: ...A0 TAP_PREQ I O SoC 2 OBSFN_A1 TAP_PRDY I O SoC 3 GND GND NA 4 OBSDATA_A 0 DBG 0 I O SoC 5 OBSDATA_A 1 DBG 1 I O SoC 6 GND GND NA 7 OBSDATA_A 2 DBG 2 I O SoC 8 OBSDATA_A 3 DBG 3 I O SoC 9 GND GND NA 1...

Page 31: ...I1_CTRDATA 3 3V 7 GND 18 GND 8 DP_LANE2 TMDS_DATA0 19 DP_HPD HDMI_HPD 9 DP_LANE2 TMDS_DATA0 20 DP_PWR only 3 3V 10 GND 21 DP_PWR only 3 3V 11 DP_LANE3 TMDS1_CLK 22 DP_PWR only 3 3V 6 5 1 Display Mode...

Page 32: ...32 6 6 Fan Connector Connector Type JVE 24W1125A 04M00 Pin Orientation 1 2 3 4 Pin Definitions Pin Signal 1 FAN_PWMOUT 2 FAN_TACHIN 3 Ground 4 5V...

Page 33: ...tandard modules will not include the FPC connector and will only route LAN signals to the X4 connector Connector Type FPC CN 1 20P RT D5 Pin Definitions Pin Orientation Pin Signal 1 GND 2 LAN_MDI_N3_C...

Page 34: ...ase refer to SEMA documentation The SW1 switch allows users to change the boot behavior of the module It sets the module to either fail safe mode or assigns SPI0 or SPI1 as the boot BIOS while providi...

Page 35: ...he following steps 1 Shut down the system 2 Press the BIOS Setup Defaults RESET Button continuously and boot up the system You can release the button when the BIOS prompt screen appears 3 The BIOS pro...

Page 36: ...uting needs to be modified This can be done with the SW4 switch Note that ABCD is the default standard ETX compliant setting Switch Settings PCI IRQ Position 1 Position 2 Comment ABCD ON OFF default D...

Page 37: ...atchdog Timer Features auto reload at power up X System Restart Cause Power loss BIOS Fail Watchdog Internal Reset External Reset X Fail safe BIOS support In case of a boot failure hardware signals te...

Page 38: ...3 3 1024 5 V3 3V MSB 8 LSB x 1 1 x 3 3 1024 6 VIN MSB 8 LSB x 6 000 x 3 3 1024 7 MAIN CURRENT Use Main Current Function 7 1 2 Main Current The BMC of the ETX BT implements a current monitor The curren...

Page 39: ...ETX BT 39 7 1 3 BMC Status This register shows the status of BMC controlled signals on the ETX BT Status Bit Signal 0 WDT_OUT 1 LVDS_VDDEN 2 LVDS_BKLTEN 3 NULL 4 POSTWDT_DISn 5 SEL_BIOS 6 NULL 7 NULL...

Page 40: ...red in the Flash Storage and is cleared when the power is removed Therefore a Clear Exception Code command is not needed or supported Exception Code Error Message 0 NOERROR 2 NO_SUSCLK 3 NO_SLP_S5 4 N...

Page 41: ...lags The BMC Flags register returns the last detected Exception Code since power up and shows the BIOS in use and the power mode Bit Description 0 4 Exception Code 6 0 AT mode 1 ATX mode 7 0 Standard...

Page 42: ...FFFFFh High BIOS 0K 1MB 1MB DOS DRAM 8 2 I O Map Hex Range Device 20h 21h 24h 25h 28h 29h 2Ch 2Dh 30h 31h 34h 5h 38h 39h 3Ch 3Dh 8259 Master 40h 43h 50h 53h 8254s 60h 64h PS2 Control 61h 63h 65h 67h N...

Page 43: ...Parallel Port LPT IRQ5 via SERIRQ PIRQ Note 1 6 Generic IRQ6 via SERIRQ PIRQ Note 1 7 Generic IRQ7 via SERIRQ PIRQ Note 1 8 Real time clock N A No 9 Generic IRQ9 via SERIRQ PIRQ Note 1 10 Generic IRQ1...

Page 44: ...A N A Note 1 12 PS 2 Mouse IRQ12 via SERIRQ PIRQ Note 1 13 N A N A Note 1 14 N A N A Note 1 15 N A N A Note 1 16 N A PCIE Port 1 2 3 4 eMMC IGD PCI Slot 1 2 3 4 Note 1 17 N A PCIE Port 1 2 3 4 SDIO De...

Page 45: ...00h 1Ch 00h Internal PCI Express Root port 1 00h 1Ch 01h Internal PCI Express Root port 2 00h 1Ch 02h Internal PCI Express Root port 3 00h 1Ch 03h Internal PCI Express Root port 4 00h 1Dh 00h Interna...

Page 46: ...1 INTB 17 INTB 17 Int2 INTC 18 Int3 INTD 19 INT Line SD Host 2 SD Card SATA Controller TI PCI to PCI Bridge xHCI Host Low Power Audio Engine TXE HDA Int0 INTE 20 INTF 21 INTF 21 INTG 22 Int1 Int2 INTC...

Page 47: ...hex Function Device A0 DDR3 channel A DDR3 socket C0 eDP to LVDS NXP3460 49 GbE LAN i211 2E Super I O W83627DHG PT 50 BMC PD78F0763 8 7 I2 C Address Table Address hex Function Device 92 System thermal...

Page 48: ...resented in bold and the function of each setting is described in the right hand column of the respective table Main Advanced Security Boot Save Exit System Information Processor Information VGA Firmw...

Page 49: ...eature Options Description CPU Brand String Info only Display CPU brand name Max CPU Speed Info only Display CPU frequency CPU Signature Info only Display CPU ID Number of Processors Info only Display...

Page 50: ...ial Number Manufacturing Date Read only Display SMC manufacturing date Last Repair Date Read only Display SMC last repair date MAC ID Read only Display SMC MAC ID SEMA Features Read only Display SEMA...

Page 51: ...s Info only Total Runtime Read only The returned value specifies the total time in minutes the system is running in S0 state Current Runtime Read only The returned value specifies the time in seconds...

Page 52: ...s in ATX Mode Turn on Remain off Last State Turn On The machine starts automatically when the power supply is turned on Remain Off To start the machine the power button has to be pressed Last State Th...

Page 53: ...2 7 System Date and Time Feature Options Description System Date Weekday MM DD YYYY Set the Date Use Tab to switch between Date elements System Time HH MM SS Set the Timer Use Tab to switch between Ti...

Page 54: ...che Info only Display cache info L3 Cache Inf o only Display cache info Limit CPUID Maximum Disabled Enabled Disabled for Windows XP Execute Disabled Bit Disabled Enabled XD can prevent certain classe...

Page 55: ...Display Interface Auto IGD PCIE Select which of IGD PCI graphics device should be primary display Integrated Graphics Device Enabled Disabled Enable Enable integrated graphics device IGD when selecte...

Page 56: ...ness 255 A change takes effect immediately The value range starts by 0 and Ends by 255 IGFX Boot Display Device VBIOS Default CRT EFP LFP Select the video device which will be activated during POST Th...

Page 57: ...IDE AHCI SATA Test Mode Enabled Disabled Test Mode enable disable SATA Controller Speed Gen1 Gen2 SATA speed support Gen1 or Gen2 SATA Port Configuration Submenu 9 3 4 1 SATA SATA Port Configuration F...

Page 58: ...without EHCI hand off support The EHCI ownership change should be claimed by the EHCI OS driver USB Mass Storage Driver Support Enabled Disabled Enable Disable USB Mass Storage Driver Support Chipset...

Page 59: ...ption Network Info only Network Stack Enabled Disabled Enable Disable UEFI network stack LAN Controller Enabled Disabled Enables Disable the PCI Express Port 3 in the Chipset 9 3 7 PCI Feature Options...

Page 60: ...erial Port Device Settings Change Settings Enabled Disabled IO 2F8h IRQ 3 Auto Standard Serial Port Mode IrDA Active pulse 1 6 uS IrDA Active pulse 3 16 bit time ASKIR Mode Enable Disable serial port...

Page 61: ...HPSIR function Enable Amplitude Shift Keyed IR Enable Disable serial port COM Fixed configuration of serial port Change the Serial Port mode Select High Speed or Normal mode mode Parallel Port Config...

Page 62: ...own message during system shutdown 9 3 10 Sound Feature Options Description Sound Info only Azalia Disabled Enabled Control Detection of the Azalia device Disabled Azalia will be unconditionally disab...

Page 63: ...ays 1 Space parity bit is always 0 Mart and Space Parity do not allow for error detection Stop Bits 1 2 Stop bits indicate the end of a serial data packet a start bit indicates the beginning The stand...

Page 64: ...of the ACPI Critical Trip Point the point in which the OS will shut the system off Active Cooling Trip Point Disabled 40 C 50 C 60 C 70 C BMC Default Active cooling trip point Passive Trip Point Disab...

Page 65: ...PCIe SATA SSC Enabled Disabled Enable Disable spread spectrum to SATA Spectrum Value 0 456 Adjust spectrum value 9 3 13 1 Miscellaneous BIOS Security Configuration Feature Options Description BIOS Se...

Page 66: ...Description System Mode Setup Secure Boot Info only Secure Boot Disabled Enabled Secure Boot can be enabled if 1 System running in User mode with enrolled Platform Key PK 2 CSM function is disabled Se...

Page 67: ...m CSM Configuration Boot option filter Csm Configuration Video Boot Option Priorities Info only Hard Drive BBS Priorities Info only CSM Parameters Submenu CSM configuration Enable Disable Option ROM e...

Page 68: ...Changes and Exit Yes No Exit system setup without saving any changes Save Changes and Reset Yes No Reset the system after saving the changes Discard Changes and Reset Yes No Reset system setup without...

Page 69: ...electrical shock and or damage to equipment Keep equipment away from water or liquid sources Keep equipment away from high heat or high humidity Keep equipment properly ventilated do not block or cov...

Page 70: ...Toll Free 1 800 966 5200 USA only Fax 1 408 360 0222 Email info adlinktech com ADLINK Technology China Co Ltd Address 300 Fang Chun Rd Zhangjiang Hi Tech Park Pudong New Area Shanghai 201203 China Tel...

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