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58

Operation Theory

level for SRC1 is ±10V and the resolution is 78mV (please refer to
Table 4-6), while the trigger range of SRC2 is the full-scale range
of the selected channel input, and the resolution is the desired
range divided by 256. For example, if the channel input selected to
be the trigger source is set bipolar and ±5V range, the trigger volt-
age would be 4.96V when the trigger level code is set to 0xFF
while 0V when the code is set to 0x80.

Figure 4-31: Analog trigger block diagram

The trigger signal is generated when the analog trigger condition
is satis-fied. There are five analog trigger conditions in the DAQ/
PXI-20XX. The DAQ/PXI-20XX uses 2 threshold voltages,
Low_Threshold and High_Threshold to build the 5 different trigger
conditions. Users could configure the trigger conditions easily by
software.

Trigger Level digital setting Trigger voltage

0xFF

9.92V

0xFE

9.84V

---

---

0x81

0.08V

0x80

0

0x7F

-0.08V

---

---

0x01

-9.92V

Table 4-7: Analog trigger SRC1 (EXTATRIG) ideal transfer characteristic

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Summary of Contents for DAQ/PXI-20 Series

Page 1: ...buy your excess underutilized and idle equipment along with credit for buybacks and trade ins Custom engineering so your equipment works exactly as you specify Critical and expedited services Leasing Rentals Demos In stock Ready to ship TAR certified secure asset solutions Expert team I Trust guarantee I 100 satisfaction All trademarks brand names and brands appearing herein are the property of th...

Page 2: ...nce Technologies Automate the World Manual Rev 2 00 Revision Date April 20 2006 Part No 50 11020 1030 DAQ PXI 201x 200x 4 CH Simultaneous High Performance Multi Function Data Acquisition Card User s Manual ...

Page 3: ...ntial damages arising out of the use or inability to use the product or documentation even if advised of the possibility of such damages This document contains proprietary information protected by copy right All rights are reserved No part of this manual may be repro duced by any mechanical electronic or other means in any form without prior written permission of the manufacturer Trademarks Produc...

Page 4: ...vice adlinktech com TEL 886 2 82265877 FAX 886 2 82265717 Address 9F No 166 Jian Yi Road Chungho City Taipei 235 Taiwan Please email or FAX this completed service form for prompt and satisfactory service Company Information Company Organization Contact Person E mail Address Address Country TEL FAX Web Site Product Information Product Model Environment OS M B CPU Chipset Bios Please give a detailed...

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Page 6: ...log Input Signal Connection 24 Types of signal sources 24 Single Ended Measurements 24 Differential Measurements 25 4 Operation Theory 27 4 1 A D Conversion 27 DAQ PXI 2010 AI Data Format 28 DAQ PXI 2005 2006 2016 AI Data Format 30 Software conversion with polling data transfer acqui sition mode Software Polling 30 Programmable scan acquisition mode 31 Trigger Modes 33 4 2 D A Conversion 42 Softwa...

Page 7: ...igger 57 4 6 User controllable Timing Signals 61 DAQ timing signals 63 Auxiliary Function Inputs AFI 64 System Synchronization Interface 67 AI_Trig_Out and AO_Trig_Out 69 5 Calibration 71 5 1 Loading Calibration Constants 71 5 2 Auto calibration 71 5 3 Saving Calibration Constants 72 ...

Page 8: ...2 digital codes are SDI 1 0 29 Table 4 3 Bipolar analog input range and the output digital code on the DAQ PXI 2005 2006 2016 30 Table 4 4 Unipolar analog input range and the output digital code on the DAQ PXI 2005 2006 2016 30 Table 4 5 Bipolar output code table Vref 10V if internal reference is selected 43 Table 4 6 Unipolar output code table Vref 10V if internal reference is selected 43 Table 4...

Page 9: ...an is in progress 37 Figure 4 10 Post trigger 38 Figure 4 11 Delay trigger 39 Figure 4 12 Post trigger with re trigger 40 Figure 4 13 Scatter gather DMA for data transfer 42 Figure 4 14 Typical D A timing of waveform generation Assuming the data in the data buffer are 2V 4V 4V 0V 45 Figure 4 15 Post trigger waveform generation Assuming the data in the data buffer are 2V 4V 6V 3V 0V 4V 2V 4V 46 Fig...

Page 10: ...ration 56 Figure 4 29 Mode 7 Operation 56 Figure 4 30 Mode 8 Operation 57 Figure 4 31 Analog trigger block diagram 58 Figure 4 32 Below Low analog trigger condition 59 Figure 4 33 Above High analog trigger condition 59 Figure 4 34 Inside Region analog trigger condition 60 Figure 4 35 High Hysteresis analog trigger condition 60 Figure 4 36 Low Hysteresis analog trigger condition 61 Figure 4 37 Exte...

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Page 12: ... 20XX is an advanced data acquisition card based on the 32 bit PCI architecture High performance designs and the state of the art technology make this card ideal for data logging and signal analysis ap plications in medical process control etc ...

Page 13: ...grammable gain x1 x2 x4 x8 for all DQ 20XX X DAQ PXI 2010 Total 8K samples A D FIFO X DAQ PXI 2005 2006 2016 Total 512 samples A D FIFO X Versatile trigger sources software trigger external digital trigger analog trigger and trigger from System Synchroniza tion Interface SSI X A D Data transfer software polling bus mastering DMA with Scatter Gather functionality X Four A D trigger modes post trigg...

Page 14: ...Introduction 3 1 2 Applications X Automotive Testing X Cable Testing X Transient signal measurement X ATE X Laboratory Automation X Biotech measurement ...

Page 15: ...0 2MS s Z 2016 800kS s Z 2005 500kS s Z 2006 250kS s X Resolution Z 2010 14 bits no missing code Z 2005 2006 2016 16 bits no missing code X FIFO buffer size Z 2010 8K samples Z 2005 2006 2016 512 samples X Programmable input range Z Bipolar 10V 5V 2 5V 1 25V Z Unipolar 0 10V 0 5V 0 2 5V 0 1 25V X Operational common mode voltage range 11V X Overvoltage protection Z Power on continuous 30V Z Power o...

Page 16: ...Hz 2006 10V 630 kHz 0 10V 640 kHz 5V 620 kHz 0 5V 620 kHz 2 5V 540 kHz 0 2 5V 540 kHz 1 25V 410 kHz 0 1 25V 420 kHz 2016 10V 840kHz 0 10V 900kHz 5V 825kHz 0 5V 800kHz 2 5V 710kHz 0 2 5V 690kHz 1 25V 530kHz 0 1 25V 530kHz Table 1 1 3dB small signal bandwidth Device Input Range System noise Input Range System noise 2010 10V 0 6 LSBrms 0 10V 0 8 LSBrms 5V 0 6 LSBrms 0 5V 0 8 LSBrms 2 5V 0 6 LSBrms 0 ...

Page 17: ... 5V 1 1 LSBrms 0 2 5V 1 7 LSBrms 1 25V 1 1 LSBrms 0 1 25V 1 8 LSBrms 2016 10V 1 6 LSBrms 0 10V 2 9 LSBrms 5V 1 8 LSBrms 0 5V 3 2 LSBrms 2 5V 1 8 LSBrms 0 2 5V 3 2 LSBrms 1 25V 1 9 LSBrms 0 1 25V 3 4 LSBrms Device Input Range System noise Input Range System noise Table 1 2 System Noise ...

Page 18: ...ror Z Before calibration 60mV max Z After calibration 1mV max X Gain error Device Input Range CMRR Input Range CMRR 2010 10V 90 dB 0 10V 89 dB 5V 92 dB 0 5V 92 dB 2 5V 95 dB 0 2 5V 94 dB 1 25V 97 dB 0 1 25V 97 dB 2005 10V 86 dB 0 10V 85 dB 5V 88 dB 0 5V 88 dB 2 5V 91 dB 0 2 5V 90 dB 1 25V 93 dB 0 1 25V 93 dB 2006 10V 87 dB 0 10V 86 dB 5V 89 dB 0 5V 88 dB 2 5V 91 dB 0 2 5V 91 dB 1 25V 93 dB 0 1 25V...

Page 19: ...8 Introduction Z Before calibration 0 6 of output max Z After calibration 0 1 of output max for DAQ PXI 2010 0 03 of output max for DAQ PXI 2005 2006 2016 ...

Page 20: ... mastering DMA with scatter gather X Output range Z Bipolar 10V or AOEXTREF Z Unipolar 0 10V or 0 AOEXTREF X Settling time 3µS to 0 5 LSB accuracy X Slew rate 20V µS X Output coupling DC X Protection Short circuit to ground X Output impedance 0 3Ω typical X Output driving current 5mA max X Stability Any passive load up to 1500pF X Power on state 0V steady state X Power on glitch 1 5V 500uS X Relat...

Page 21: ...tage Z Low VOL 0 5V max IOL 8mA max Z High VOH 2 7V min IOH 400µA X Synchronous Digital Inputs SDI for DAQ PXI 2010 only X Number of channels 8 digital inputs sampled simulta neously with the analog signal input X Compatibility TTL CMOS X Input voltage Z Logic Low VIL 0 8V max IIL 0 2mA max Z Logic High VIH 2 7V min IIL 0 02mA max General Purpose Timer Counter GPTC X Number of channel 2 Up Down Ti...

Page 22: ...Analog Trigger Input EXTATRIG X Input Impedance Z 40kΩ for DAQ PXI 2010 Z 2kΩ for DAQ PXI 2005 2006 2016 X Coupling DC X Protection Continuous 35V maximum Digital Trigger D Trig X Compatibility TTL CMOS X Response Rising or falling edge X Pulse Width 10ns min System Synchronous Interface SSI X Trigger lines 7 Stability X Recommended warm up time 15 minutes X On board calibration reference Z Level ...

Page 23: ...r Requirement typical X 5VDC 1 82 A for DAQ PXI 2010 Z 2 04 A for DAQ PXI 2005 Z 1 82 A for DAQ PXI 2006 Z 2 52 A for DAQ PXI 2016 Operating Environment X Ambient temperature 0 to 55 C X Relative humidity 10 to 90 non condensing Storage Environment X Ambient temperature 20 to 80 C X Relative humidity 5 to 95 non condensing Interface Connector 68 pin AMP 787254 1 or equivalent ...

Page 24: ...evice drivers and DLL for Windows 98 NT 2000 XP DLL is binary compatible across Windows 98 NT 2000 XP This means all applications developed with D2K DASK are compatible across Windows 98 NT 2000 XP The developing environment can be VB VC Delphi BC5 or any Windows programming language that allows calls to a DLL The user s guide and function reference manual of D2K DASK are in the CD Manual Software...

Page 25: ...he card Please refer to the Software Installation Guide in the package to install these drivers In addition ADLINK supplies ActiveX control software DAQBench DAQBench is a collection of ActiveX controls for measurement or auto mation applications With DAQBench you can easily develop custom user interfaces to display your data analyze data you acquired or received from other sources or integrate wi...

Page 26: ... contact the dealer from whom you purchased the product Save the shipping materi als and carton in case you want to ship or store the product in the future 2 2 Unpacking Your DAQ PXI 20XX SERIES card contains electro static sensi tive com ponents that can be easily be damaged by static electric ity Therefore the card should be handled on a grounded anti static mat The operator should be wearing an...

Page 27: ...mages Press down on all the socketed IC s to make sure that they are properly seated Do this only with the module place on a firm flat surface You are now ready to install your DAQ PXI 20XX Note DO NOT APPLY POWER TO THE CARD IF IT HAS BEEN DAMAGED ...

Page 28: ...Installation 17 2 3 DAQ PXI 20XX Layout Figure 2 1 PCB Layout of the DAQ 20XX Figure 2 2 PCB Layout of the PXI 20XX ...

Page 29: ...d basis for all PCI boards on your system Because configuration is con trolled by the system and software there is no jumper setting required for base address DMA and interrupt IRQ The configuration is subject to change with every boot of the sys tem as new boards are added or removed 3 Troubleshooting If your system doesn t boot or if you experience erratic opera tion with your PCI board in place...

Page 30: ...SI System Synchronous Interface in DAQ 20XX The pin assign ments of the connectors are defined in Table 3 1 and Table 3 2 CH0 1 35 CH0 CH1 2 36 CH1 CH2 3 37 CH2 CH3 4 38 CH3 EXTATRIG 5 39 AIGND DA1OUT 6 40 AOGND DA0OUT 7 41 AOGND AOEXTREF 8 42 AOGND SDI3_1 NC 9 43 SDI3_0 NC SDI2_1 NC 10 44 SDI2_0 NC SDI1_1 NC 11 45 SDI1_0 NC SDI0_1 NC 12 46 SDI0_0 NC AO_TRIG_OUT 13 47 EXTWFTRG AI_TRIG_OUT 14 48 EX...

Page 31: ...nput Differential posi tive input for AI channel 0 3 5 EXTATRIG AIGND Input External AI ana log trigger 6 DA0OUT AOGND Output AO channel 0 7 DA1OUT AOGND Output AO channel 1 8 AOEXTREF AOGND Input External refer ence for AO channels 9 12 SDI 3 0 _1 2010 NC 2005 2006 2016 DGND Input Synchronous dig ital inputs 13 AO_TRIG_OUT DGND Output AO trigger signal 14 AI_TRIG_OUT DGND Output AI trigger signal...

Page 32: ...grammable DIO pins of 8255 Port C 31 65 32 66 33 67 34 68 PA 7 0 DGND PIO Programmable DIO pins of 8255 Port A 35 38 CH 0 3 Input Differential nega tive input for AI channel 0 3 39 AIGND Analog ground for AI 40 42 AOGND Analog ground for AO 43 46 SDI 3 0 _0 2010 NC 2005 2006 2016 DGND Input Synchronous dig ital inputs 47 EXTWFTRIG DGND Input External AO waveform trigger 48 EXTDTRIG DGND Input Exte...

Page 33: ...nality SSI_TIMEBASE SSI master send the TIMEBASE out SSI slave accept the SSI_TIMEBASE to replace the internal TIMEBASE signal SSI_ADCONV SSI master send the ADCONV out SSI slave accept the SSI_ADCONV to replace the internal ADCONV signal SSI_SCAN_START SSI master send the SCAN_START out SSI slave accept the SSI_SCAN_START to replace the internal SCAN_START signal SSI_AD_TRIG SSI master send the i...

Page 34: ...he DAWR out SSI slave accept the SSI_DAWR to replace the internal DAWR signal SSI_DA_TRIG SSI master send the DA_TRIG out SSI slave accept the SSI_DA_TRIG as the digital trigger signal SSI timing signal Functionality Table 3 4 Legend of SSI connector ...

Page 35: ...n ground point with respect to the DAQ PXI 20XX assuming that the computer is plugged into the same power system Non isolated out puts of instruments and devices that plug into the buildings power system are ground referenced signal sources Floating Signal Sources A floating signal source means it is not connected in any way to the buildings ground system A device with an isolated output is a floa...

Page 36: ...ons are necessary Differential Measurements Differential Connection for Grounded Reference Signal Sources The differential analog input provides two inputs that respond to the signal voltage difference between them If the signal source is ground referenced the differential mode can be used for the common mode noise rejection Figure 3 2 shows the connection of ground referenced signal sources under...

Page 37: ...ide a bias return path The resistor value should be about 100 times the equivalent source impedance If the source imped ance is less than 100ohms you can simply connect the nega tive side of the signal to AGND as well as the negative input of the Instru mentation Amplifier without any resistors at all In differential input mode less noise couples into the signal con nections than in single ended m...

Page 38: ... design we still use scan as the unit of A D data acquisition All the DA and GPTC functions are the same in DAQ PXI 20XX and DAQ PXI 22XX while DAQ PXI 25XX pro vides im proved DA timing comparing the former 2 series 4 1 A D Conversion When using an A D converter users should first know about the properties of the signal to be measured Users can decide which channel to use and where to connect the...

Page 39: ...h four digital sig nals The data format of every acquired 16 bit data is as fol lows D13 D12 D11 D1 D0 b1 b0 Where D13 D12 D11 D1 D0 2 s complement A D 14 bit data b1 b0 Synchronous Digital Inputs SDI 1 0 Figure 4 1 Synchronous Digital Inputs Block Diagram Figure 4 2 Synchronous Digital Inputs timing Note Since the analog signal is sampled when an A D conversion starts falling edge of A D_conversi...

Page 40: ...9 9988V 4 9994V 2 4997V 1 2499V 1FFF Midscale 1LSB 1 22mV 0 61mV 0 305mV 0 153mV 0001 Midscale 0V 0V 0V 0V 0000 Midscale 1LSB 1 22mV 0 61mV 0 305mV 0 153mV 3FFF FSR 10V 5V 2 5V 1 25V 2000 Table 4 1 Bipolar analog input range and the output digital code on DAQ PXI 2010 Note that the last 2 digital codes are SDI 1 0 Description Unipolar Analog Input Range Digital code Full scale Range 0V to 10V 0 to...

Page 41: ... Input Range Digital code Full scale Range 10V 5V 2 5V 1 25V Least significant bit 305 2uV 152 6uV 76 3uV 38 15uV FSR 1LSB 9 999695V 4 999847V 2 499924V 1 249962V FFFF Midscale 1LSB 305 2uV 152 6uV 76 3uV 38 15uV 8001 Midscale 0V 0V 0V 0V 8000 Midscale 1LSB 305 2uV 152 6uV 76 3uV 38 15uV 7FFF FSR 10V 5V 2 5V 1 25V 0000 Table 4 3 Bipolar analog input range and the output digital code on the DAQ PXI...

Page 42: ...ge Example Typically you can set the input configuration for different chan nels Ch1 with unipolar 10V Ch2 with bipolar 2 5V Ch3 with no signal input disabled Ch4 with bipolar 1 25V Programmable scan acquisition mode Scan Timing and Procedure It s recommended that this mode be used if your applications need a fixed and precise A D sampling rate You can accu rately program the period between conver...

Page 43: ...which use TIMEBASE as the clock source By software you can specify the TIMEBASE to be either an internal clock source on board 40MHz clock or an external clock input EXTTIMEBASE on J5 connector 68 pin VHDCI The external TIMEBASE is useful when you want to ac quire data at rates not available with the internal A D sample clock The external clock source should generate TTL compatible continuous cloc...

Page 44: ...ed condition is detected on the selected trigger source For example a rising edge on the external digital trigger input Please refer to section 4 6 for more information about SSI signals There are 4 trigger modes pre trigger post trigger middle trigger and delay trigger working with the 4 trigger sources to initiate dif ferent scan data acquisition timing when a trigger event occurs They are descr...

Page 45: ...when a conversion is in progress the data acquisition won t stop until this conversion is completed and the stored M scans of data include the last scan as illustrated in Figure 4 5 where M_counter M 3 PSC_counter 0 Figure 4 5 Pre trigger scan acquisition trigger occurs when a conversion is in progress When the trigger signal occurs before the first M scans of data are con verted the amount of sto...

Page 46: ...r pre trigger mode as illustrated in Figure 4 7 However if M_enable is set to 0 the trigger signal will be accepted any time as illustrated in Figure 13 Note that the total amount of stored data will always be equal to the number in the M_counter because the data acquisition won t stop until a scan is completed Figure 4 6 Pre trigger with M_enable 0 Trigger occurs before M scans Figure 4 7 Pre tri...

Page 47: ...mode the number of stored data could be less than the specified amount of data M N if an external trigger occurs before M scans of data are converted The M_enable bit in middle trigger mode takes the same effect as in pre trigger mode If M_enable is set to 1 the trigger signal will be ignored until the first M scans of data are converted and it assures the user with M N scans of data under middle ...

Page 48: ...f Pre Trigger In Middle trigger M_Counter ends counting before the trigger event while in Pre Trigger M_Counter ends counting right at or before trigger event Please refer to Figure 4 6 and Fig ure 4 9 Post Trigger Acquisition Use post trigger acquisition in applications where you want to col lect data after a trigger event The number of scans after the trig ger is specified in PSC_counter as illu...

Page 49: ...er event The delay time is controlled by the value which is pre loaded in the Delay_counter 16bit The counter counts down on the rising edge of the Delay_counter clock source after the trigger condition is met The clock source can be soft ware programmed either by the TIMEBASE clock 40MHz or A D sampling clock TIMEBASE SI_counter When the count reaches 0 the counter stops and the card starts to ac...

Page 50: ...p plications where you want to collect data after several trigger events The number of scans after each trigger is specified in PSC_counter and users could program Retrig_no to specify the re trigger numbers Figure 4 12 il lus trates an example In this example 2 scans of data is acquired after the first trigger signal then the card waits for the re trigger signal re trigger signals which occur bef...

Page 51: ...tering DMA provides the fastest data transfer rate on PCI bus Once the analog input operation starts control returns to your program The hardware temporarily stores the acquired data in the on board AD Data FIFO and then transfers the data to a user defined DMA buffer memory in the computer Please note that even when the acquired data length is less than the Data FIFO the AD data will not be kept ...

Page 52: ... to allocate a large continuous memory block to do the DMA transfer Therefore the PLX IOP 480 provides the function of scatter gather or chaining mode DMA to link the non continuous memory blocks into a linked list so that users can transfer very large amounts of data without being limited by the fragment of small size memory Users can configure the linked list for the input DMA channel or the out...

Page 53: ...lets users fully utilize the multiply ing characteristics of the D A converters Internal 10V reference and external reference inputs are available in the DAQ PXI 20XX The range of the D A output is directly related to the reference The digital codes that are up dated to the D A converters will mul tiply with the reference to generate the analog output While using internal 10V reference the full ra...

Page 54: ...d including timing trig ger source con trol trigger modes and data transfer methods Either mode may be ap plied to D A channels independently You can software update DA CH0 while generate timed waveforms on CH1 at the same time Software Update This is the easiest way to generate D A output First users should specify the D A output channels set output polarity unipolar or Digital Code Analog Output...

Page 55: ...gram the update period of the D A converters The D A output timing is provided through a combination of counters in the FPGA on board There are totally 5 counters to be specified These counters are UI_counter 24 bits specify the DA Update Interval CHUI_counter TIMEBASE UC_counter 24 bits specify the total Update Counts in a single waveform IC_counter 24 bits specify the Iteration Counts of wavefor...

Page 56: ... 1MHz Therefore the min imum setting of the UI_counter is 40 while using an internal TIMEBASE 40MHz Trigger Modes Post Trigger Generation Use post trigger when you want to perform DA waveform right after a trigger event occurs In this trigger mode DLY1_Counter is not used and you don t need to specify it Figure 4 15 shows a sin gle waveform generated right after a trigger signal is detected The tr...

Page 57: ...from the trigger signal to the start of the waveform generation DLY1_counter counts down on the rising edge of its clock source after the trigger condition is met When the count reaches 0 the counter stops and the DAQ PXI 20XX starts the waveform generation This DLY1_Counter is 16 bit s wide and users can set the delay time in units of TIMEBASE delay time DLY1_Counter TIMEBASE or in units of updat...

Page 58: ...h re trigger function when you want to generate waveform after more than one trigger events The re trigger function can be enabled or disabled by software setting In Figure 4 17 each trigger signal will initiate a waveform generation However the trigger event would be ignored while the waveform generation is ongoing Figure 4 17 Re triggered waveform generation Assuming the data in the data buffer ...

Page 59: ...the host PC memory to the FIFO on board the data in the FIFO will be automatically re transmitted whenever a single waveform is completed Therefore it won t occupy the PCI bandwidth when repetitive waveforms are performed However if the size of a single waveform were larger than that of the FIFO it needs to be intermittently loaded from the host PC s memory via DMA when a repetitive waveforms is p...

Page 60: ...diversify the D A waveform generation we add a DLY2 Counter to separate 2 consecutive waveforms in repetitive waveform generation The time between two waveforms is set by the value of DLY2 Counter The Delay2 counter starts to count down after a waveform generation finishes and the next waveform generation starts right after it counts down to zero just as shown in Figure 21 This DLY2_Counter is 16 ...

Page 61: ... Figure 4 21 for an example since UC_counter is set to 4 the total DA update counts that is number of pulses of DAWR signal must be a multiple of 4 update counts 20 in this example In stop mode III after a software stop command is given the waveform generation won t stop until the performed number of waveforms is a mul tiple of IC_Counter Take Figure 4 22 for an example since IC_Counter is set to ...

Page 62: ...p The 24 line GPIO are separated into three ports Port A Port B and Port C High nibble bit 7 4 and low nibble bit 3 0 of each port can be indi vidually programmed to be either inputs or outputs Upon system startup or reset all the GPIO pins are reset to high impedance inputs DAQ PXI 2010 also provides 2 digital inputs per channel SDI from J5 which are sampled simultaneously with an analog signal ...

Page 63: ...rcuit operation Timer Counter functions basics Each timer counter has three inputs that can be controlled via hardware or software They are clock input GPTC_CLK gate input GPTC_GATE and up down control input GPTC_UPDOWN The GPTC_CLK input provides a clock source input to the timer counter Active edges on the GPTC_CLK input make the counter increment or decrement The GPTC_UPDOWN input controls whet...

Page 64: ... on the GPTC_CLK after the software start Initial count can be loaded from software Current count value can be read back by soft ware any time without affecting the counting GPTC_GATE is used to enable disable counting When GPTC_GATE is inac tive the counter halts the current count value Figure 4 23 illus trates the operation with initial count 5 count down mode Figure 4 23 Mode 1 Operation Mode 2...

Page 65: ...ges on GPTC_CLK when GPTC_GATE is in its active state After the completion of the pulse width interval on GPTC_GATE GPTC_OUT out puts high and then current count value can be read back by soft ware Figure 4 25 illustrates the operation where initial count 0 count up mode Figure 4 25 Mode 3 Operation Mode 4 Single Gated Pulse Generation This mode generates a single pulse with programmable delay and...

Page 66: ... Pulse Generation This function generates a single pulse with programmable delay and pro grammable pulse width following an active GPTC_GATE edge You could specify these programmable parameters in terms of periods of the GPTC_CLK input Once the first GPTC_GATE edge triggers the single pulse GPTC_GATE takes no effect until the software start is re exe cuted Figure 4 27 illustrates the generation of...

Page 67: ...es the gener ation of two pulses with a pulse delay of two and a pulse width of four Figure 4 28 Mode 6 Operation Mode 7 Single Triggered Continuous Pulse Generation This mode is similar to mode5 except that the counter gener ates con tinuous periodic pulses with programmable pulse interval and pulse width following the first active edge of GPTC_GATE Once the first GPTC_GATE edge triggers the coun...

Page 68: ...d SSI trig gers Users can configure the trigger source by software for A D and D A processes individually Note that the A D and the D A conversion share the same analog trigger Software Trigger This trigger mode does not need any external trigger source The trigger asserts right after you execute the specified function calls to begin the operation A D and D A processes can receive an individual so...

Page 69: ... is set to 0xFF while 0V when the code is set to 0x80 Figure 4 31 Analog trigger block diagram The trigger signal is generated when the analog trigger condition is satis fied There are five analog trigger conditions in the DAQ PXI 20XX The DAQ PXI 20XX uses 2 threshold voltages Low_Threshold and High_Threshold to build the 5 different trigger conditions Users could configure the trigger conditions...

Page 70: ...ndition Figure 4 33 shows the above high analog trigger condition the trigger signal is generated when the input analog signal is higher than the High_Threshold voltage and the Low_Threshold setting is not used in this trigger condition Figure 4 33 Above High analog trigger condition Inside Region analog trigger condition Figure 4 34 shows the inside region analog trigger condition the trigger sig...

Page 71: ...alog signal level is greater than the High_Threshold voltage and the Low_Threshold voltage determines the hysteresis duration Note the High_Threshold setting should be always higher then the Low_Threshold voltage setting Figure 4 35 High Hysteresis analog trigger condition Low Hysteresis analog trigger condition Figure 4 36 shows the low hysteresis analog trigger condition the trigger signal is ge...

Page 72: ... the EXT DTRIG or the EXTWFTRG of the 68 pin connector for external digital trigger The EXTDTRIG is dedicated for A D process and the EXTWFTRG is used for D A process Users can pro gram the trigger polarity through ADLINK s software drivers easily Note that the signal level of the external digital trigger signals should be TTL compatible and the minimum pulse is 20ns Figure 4 37 External digital t...

Page 73: ...I 20XX the user controllable timing signals would be slightly differ ent However the SSI PXI timing signals remain the same for every DAQ PXI 20XX card We implemented signal multiplexers in the FPGA to individually choose the desired timing signals for the DAQ operations as shown in the Figure 4 38 Figure 4 38 DAQ signals routing Users can utilize the flexible timing signals through our software d...

Page 74: ...he following ADCONV signals for AD conversion and could come from the internal SI_counter AFI 0 and SSI_AD_START This signal is synchronous to the TIMEBASE Note that the AFI 0 should be TTL compat ible and the minimum pulse width should be the pulse width of the TIMEBASE to guarantee correct functional ities 4 ADCONV the conversion signal to initiate a single con version which could be derived fro...

Page 75: ...dge sensitive When using AFI 1 as the external DAWR source each rising edge of AFI 1 would bring an effective update sig nal Also note that the AFI 1 signal should be TTL com patible and the minimum pulse width is 20ns Auxiliary Function Inputs AFI Users could use the AFI in applications that take advantage of external circuitry to directly control the DAQ PXI 2000 series cards The AFI in cludes 2...

Page 76: ...D operation 1 TTL compatible 2 Minimum pulse width 20ns 3 Rising edge or fall ing edge EXTWFTRG External digi tal trigger input for D A operation 1 TTL compatible 2 Minimum pulse width 20ns 3 Rising edge or fall ing edge Multi function input AFI 0 Dual functions Replace the internal ADCONV 1 TTL compatible 2 Minimum pulse width 20ns 3 Rising edge sensi tive only Replace the internal SCAN_STAR T 1 ...

Page 77: ...ONV signal then the SI_counter and the internally generated SCAN_START will not be effective By controlling the ADCONV externally users can sample the data ac cording to external events In this mode the Trigger signal and trigger mode settings will are not avail able AFI 0 could also be used as SCAN_START signal for A D operations Please refer to sections 4 1 and 4 6 1 for detailed descriptions of...

Page 78: ...signal Functionality SSI_TIMEBASE SSI master send the TIMEBASE out SSI slave accept the SSI_TIMEBASE to replace the internal TIMEBASE signal Note Affects on both A D and D A opera tions SSI_AD_TRIG SSI master send the internal AD_TRIG out SSI slave accept the SSI_AD_TRIG as the digital trigger signal SSI_ADCONV SSI master send the ADCONV out SSI slave accept the SSI_ADCONV to replace the internal ...

Page 79: ...on of the PXI specifications please refer to PXI specification Re vision 2 0 from PXI System Alliance www pxisa org The 6 internal timing signals could be routed to the SSI or the PXI trigger bus through software drivers Please refer to section 4 6 1 for detailed in formation of the 6 internal timing signals Physically the signal routings are accomplished in the FPGA Cards that are connected toget...

Page 80: ...he SSI PXI connectors Thus we can achieve 16 channel acquisition simultaneously You could arbitrarily choose each of the 6 timing signals as the SSI master from any one of the cards The SSI master can output the internal timing signals to the SSI slaves With the SSI users could achieve better card to card synchronization Note that when power up or reset the DAQ timing signals are reset to use the ...

Page 81: ...70 Operation Theory VHDCI Connecting them to any signal source may cause per manent damage ...

Page 82: ...on con stants there are three extra user modifiable banks This means users can load the TrimDACs values either from the original fac tory calibration or from a calibration that is subsequently per formed Because of the fact that errors in measurements and outputs will vary with time and temperature it is recommended re calibratation when the card is installed in the users environment The auto cali...

Page 83: ...tiated because the DA outputs would be changed in the process of calibration 5 3 Saving Calibration Constants After an auto calibration is completed users can save the new cal ibration constants into one of the three user modifiable banks in the EEPROM The date and the temperature when you ran the auto calibration will be saved accompanied with the calibration constants This means users can store ...

Page 84: ...d party products not manufactured by ADLINK will be covered by the original manufactur ers warranty X For products containing storage devices hard drives flash cards etc please back up your data before send ing them for repair ADLINK is not responsible for any loss of data X Please ensure the use of properly licensed software with our systems ADLINK does not condone the use of pirated software and...

Page 85: ...of battery fluid during or after change of batteries by customer user X Damage from improper repair by unauthorized ADLINK technicians X Products with altered and or damaged serial numbers are not entitled to our service X This warranty is not transferable or extendible X Other categories not protected under our warranty 4 Customers are responsible for shipping costs to transport damaged products ...

Page 86: ...quipment Have surplus equipment taking up shelf space We ll give it a new home Learn more Visit us at artisantg com for more info on price quotes drivers technical specifications manuals and documentation Artisan Scientific Corporation dba Artisan Technology Group is not an affiliate representative or authorized distributor for any manufacturer listed herein We re here to make your life easier How...

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