ADLINK Technology cPCI-6765, User Manual

Page: 42 / 82

34 Backplanes
3.2 cBP-6405R (64-bit/66MHz)
The backplane for the cPCIS-6400 Series 6U 64-bit, 5-slot chassis
is the cBP-6405R, a 6U 64-bit, 5-slot, H.110 CompactPCI back-
plane with rear I/O.
Features
X
Standard CompactPCI 3U height for 6U cPCI cards
X
Supports 80mm rear I/O for each slot
X
Suitable for one single/dual-slot system module and four
expansion cards
X
Supports PICMG 2.5 H.110 CT Bus
X
PICMG 2.1 Hot Swap compliant 64-bit 5-slot CompactPCI
backplane with P3 & P5 rear I/O
Specifications
X
CompactPCI Compliancy
Z
PICMG 2.0 CompactPCI core specification R3.0
Z
PICMG 2.1 CompactPCI hot swap R2.0
Z
PICMG 2.5 CompactPCI Computer Telephony R1.0
X
Dimension: 262.05 x 120.9 (mm, W x H)
X
PCI bus clock: up to 64-bit/66MHz
X
System slot rear I/O: P3, P4 and P5 rear I/O with AB type
shroud
X
Peripheral slots: four
X
H.110 bus: Compliant with PICMG 2.5, for all peripheral
slots
X
V (I/O): 3.3V or 5V selectable, default 5V
X
Power Connectors: ATX connector x1, DC screw terminals
X
System slot legacy I/O: FDD, IDE1, and IDE2 (pin compati-
ble with cPCI-6760Dand cPCI-6780 only)
X
Other connectors: INH#, Reset, PWR_FAL#, Voltage LEDs,
H.110 Power Pairs (VRG, Vbat)