44
Board Interfaces
Leading
EDGE COMPUTING
PMC Clock Settings (SW_PMC1)
Switch SW_PMC1 allows the user to force the PCI bus to lower
bandwidth and clock settings. All are set to OFF by default to
support PCI-X mode up to 64-bit/133MHz maximum with the
bandwidth and clock determined by the PCI device attached.
For SKUs with two PMC slots, both slots will have the same
clock settings.
Pin
On
Off
1
Force the PCI bandwidth to
32-bit
Auto Negotiation
2
Force the PCI clock to
PCI 66MHz
3
Force the PCI bus to PCI mode
(no PCI-X mode support)
4
Force the PCI clock to
PCI-X
100MHz
ON
1
2
3 4
Summary of Contents for cPCI-6530BL Series
Page 8: ...viii Table of Contents Leading EDGE COMPUTING This page intentionally left blank ...
Page 10: ...x List of Figures Leading EDGE COMPUTING This page intentionally left blank ...
Page 12: ...xii List of Tables Leading EDGE COMPUTING This page intentionally left blank ...
Page 16: ...4 Introduction Leading EDGE COMPUTING This page intentionally left blank ...
Page 24: ...12 Specifications Leading EDGE COMPUTING This page intentionally left blank ...
Page 68: ...56 Getting Started Leading EDGE COMPUTING This page intentionally left blank ...
Page 76: ...64 Utilities Leading EDGE COMPUTING This page intentionally left blank ...
Page 110: ...98 BIOS Setup Utility Leading EDGE COMPUTING 8 4 2 PCH IO Configuration ...