ADLINK Technology CoreModule 720 Reference Manual Download Page 45

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Chapter 4

BIOS Setup

CoreModule 720

Reference Manual

•

VGA Palette Snoop [

Disabled

; Enabled]

•

PERR# Generation [

Disabled

; Enabled]

•

SERR# Generation [

Disabled

; Enabled]

♦

PCI Express Device Settings

•

Relaxed Ordering [

Disabled

; Enabled]

•

Extended Tag [

Disabled

; Enabled]

•

No Snoop [Disabled;

Enabled

]

•

Maximum Payload [

Auto

; 128 Bytes; 256 Bytes; 512 Bytes; 1024 Bytes; 2048 Bytes;

4096 Bytes]

•

Maximum Read Request [

Auto

; 128 Bytes; 256 Bytes; 512 Bytes; 1024 Bytes; 2048 Bytes;

4096 Bytes]

♦

PCI Express Link Settings

•

Automatic ASPM [

Disabled

; Auto; Force L0]

WARNING: Enabling ASPM may cause some PCI-E devices to fail

•

Extended Synch [

Disabled

; Enabled]

•

CPU Configuration

♦

Processor Type Genuine Intel(R) CPU

♦

EMT64 Supported

♦

Processor Speed XXXX MHz

♦

Ratio Status XX

♦

Actual Ratio XX

♦

System Bus Speed XXX MHz

♦

Processor Stepping XXXXX

♦

Microcode Revision XXX

♦

L1 Cache RAM XX k

♦

L2 Cache RAM XXX k

♦

Processor Core Single

♦

Hyper-Threading Supported

♦

Intel SpeedStep [Disabled;

Enabled

]

♦

Hyper-Threading [Disabled;

Enabled

]

♦

Execute Disable Bit [Disabled;

Enabled

]

♦

Limit CPUID Maximum [

Disabled

; Enabled]

♦

Intel Virtualization [

Disabled

; Enabled]

♦

C-States [Disabled;

Enabled

]

♦

Enhanced C1 [

Disabled

; Enabled]

♦

Enhanced C2 [Disabled;

Enabled

]

♦

Enhanced C3 [

Disabled

; Enabled]

♦

Enhanced C4 [Disabled;

Enabled

]

Summary of Contents for CoreModule 720

Page 1: ...CoreModule 720 Single Board Computer Reference Manual P N 50 1Z105 1000 ...

Page 2: ...the bottom of this page Audience This manual provides reference only for computer design engineers including but not limited to hardware and software designers and applications engineers ADLINK Technology Inc assumes you are qualified to design and implement prototype computer equipment ii Reference Manual CoreModule 720 TRADEMARKS CoreModule and the Ampro logo are registered trademarks and ADLINK...

Page 3: ...ications 16 Environmental Specifications 16 Thermal Cooling Requirements 17 Chapter 3 Hardware 19 Overview 19 CPU 20 Graphics 20 Memory 20 Interrupt Channel Assignments 21 Memory Map 21 I O Address Map 22 Serial Interfaces 23 USB Interfaces 24 Ethernet Interface 26 Video SDVO LVDS Interfaces 27 Power Interface 29 User GPIO Interface 29 Utility Interface 30 Power Button 30 Reset Switch 30 Speaker 3...

Page 4: ...Side 10 Figure 2 5 Connector Pin Sequences 12 Figure 2 6 Header Connector and Socket Locations Top Side 12 Figure 2 7 Jumper Header Locations Top Side 13 Figure 2 8 Mechanical Overview Top Side 15 Figure 2 9 Stack Height of Cooling Assembly 17 Figure 3 1 Oops Jumper Serial Port DB9 33 Figure 3 2 Serial Console Jumper 34 Figure 4 1 Main BIOS Setup Screen 37 Figure 4 2 Advanced BIOS Setup Screen 38 ...

Page 5: ... SDVO Interface Pin Signals J15 27 Table 3 11 LVDS Video Interface Pin Signals J23 28 Table 3 12 Power Interface Pin Signals J19 29 Table 3 13 User GPIO Interface Pin Signals J3 29 Table 3 14 Utility Interface Pin Signals J22 30 Table 3 15 SMBus Reserved Addresses 31 Table 3 16 SMBus Pin Signals J24 31 Table 3 17 CAN Interface Pin Signals J4 31 Table 3 18 I2C Interface Pin Signals J6 32 Table 3 19...

Page 6: ...Contents vi Reference Manual CoreModule 720 ...

Page 7: ...al definitions for industry standard interfaces References The following list of references may help you successfully complete your custom design Expansion Bus Specifications PC 104 Specification Revision 2 5 November 2003 PC 104 Plus Specification Revision 2 0 November 2003 Web site http www pc104 org PCI Specification Revision 3 0 August 12 2002 Web site http www pcisig com LPC Bus Specification...

Page 8: ...tmel Corporation and the AT25128B SSHL B Ethernet EEPROM Data sheet http www atmel com dyn resources prod_documents doc8535 pdf Fintek and the F85226FG LPC to ISA Bridge Data sheet http pdf1 alldatasheet com datasheet pdf view 257962 FINTEK F85226FG html PLX Technology and the PEX8112 PCIe to PCI Bridge Data sheet http www plxtech com products expresslane pex8112 technicaldocumentation Atmel Corpo...

Page 9: ...igh speed digital I O Data Acquisition Analog In Out USB 2 0 expansion modules IEEE 1394 FireWire expansion modules Standard VGA video output PC 104 or PC 104 Plus expansion modules can be stacked with the CoreModule 720 avoiding the need for large expensive card cages and backplanes The PC 104 Plus expansion modules can be mounted directly to the PC 104 and PC 104 Plus connectors of the CoreModul...

Page 10: ...he CPU through the PCIe Port0 and a Gigabit Ethernet controller connects to the CPU through PCIe Port2 The CoreModule 720 can be expanded through the LPC and PCIe expansion buses using the PC 104 and PC 104 Plus connectors for additional system functions These buses offer compact self stacking modular expandability The PC 104 bus is an embedded system version of the signal set provided on a deskto...

Page 11: ...nbuffered memory Expansion Buses PC 104 bus speeds up to 14MHz 16 bit ISA Bus PC 104 Plus bus speed at up to 66MHz 32 bit PCI Bus PCI 3 0 bus I2C 2 1 bus Bosch CAN protocol version 2 0B Active SATA Interface Supports two SATA ports from the EG20T PCH one used for SSD Provides one standard SATA connector Supports on board Solid State Drive SSD with default 8GB capacity Serial Interface Provides fou...

Page 12: ...control Supports full duplex or half duplex mode Full duplex mode supports transmit and receive frames simultaneously Supports IEEE 802 3x Flow control in full duplex mode Half duplex mode supports enhanced proprietary collision reduction mode Video Interfaces SDVO and LVDS Provide SDVO outputs Resolutions up to 1280x1024 85Hz A variety of external display technologies such as DVI TV Out and CRT M...

Page 13: ...nector PCH EG20T Platform Controller Hub Intel CS82TPCF LVDS Header SDVO Connector Memory Bus ISA Bus PCI Bus CAN Header COM0 Header RS 232 Transceiver LPC Bus PCIe Bus Port 1 PCIe Bus Port 0 USB Header USB Header USB 2 USB Header USB 2 USB 2 Serial 1 Serial 2 SPI Flash GPIO Header SATA0 SATA1 SPI GPIO I2C Header I2C SMBus Header Utility Header Solid State Drive SDIO SD Socket SATA0 Connector RS 2...

Page 14: ...nsfer PCH Platform Controller Hub U10 Intel CS82TPCF PCH EG20T I O Hub for common user interfaces Provides Southbridge interfaces and off loads some Northbridge functions from the CPU CAN Transceiver U12 on bottom side see Figure 2 4 Texas Instruments SN65HVD1040D Transceiver for Controller Area Network CAN Provides up to 1 Mbps of differential transmit and receive capabilities for the CAN control...

Page 15: ...re 2 4 AME AME8850AEEVADJZ Linear Regulator Provides power saving mode over current protection and thermal shutdown for the PCIe to PCI Bridge Temperature Monitor U33 Analog Devices ADM1032ARMZ Digital thermometer for CPU temperature Measures the temperature output of the CPU and provides over temperature alarm Thermal Regulator SSD U35 AME AME8850AEEVADJZ Linear Regulator Provides power saving mo...

Page 16: ...nsceiver COM0 U22 RS 232 Transceiver COM1 3 U31 SPI Flash BIOS U33 Temperature Monitor U35 Thermal Regulator SSD T1 Gigabit Ethernet Transformer U16 U31 U15 U3 U2 U4 U18 U22 U21 U35 U10 U5 T1 U1 U33 CM720_Bottom_Comp_a Key U6 DDR2 SDRAM 2 U7 DDR2 SDRAM 2 U8 DDR2 SDRAM 2 U9 DDR2 SDRAM 2 U12 CAN Transceiver U17 LPC to ISA Bridge U20 SPI EEPROM PCIe to PCI U32 Thermal Regulator PCIe to PCI U37 Solid ...

Page 17: ... J10 Serial 1 Top 10 pin 0 079 2mm shrouded header for the COM0 signals J11 Serial 2 Top 10 pin 0 079 2mm shrouded header for the COM1 2 and 3 signals J12 USB 0 1 Top 10 pin 0 079 2mm shrouded header for USB0 and USB1 signals J13 USB 4 5 Top 10 pin 0 079 2mm shrouded header for USB4 and USB5 signals J14 USB 2 3 Top 10 pin 0 079 2mm shrouded header for USB2 and USB3 signals J15 SDVO Top 30 pin 0 02...

Page 18: ...rs represent pin 1 Black square pins on right angle headers represent pin 2 in top side views and pin 1 in bottom side views 1 2 3 4 5 6 7 8 9 10 10 pin two rows Odd Even 1 2 CM720_ConNum_a CM720_Top_Conn_a Key J1 LPC J3 GPIO J4 CAN J5 SD Memory Socket Bottom J6 I2C J7 SATA0 J8 Ethernet Gigabit J9 Ethernet LED Gigabit J10 Serial 1 COM 0 J11 Serial 2 COM 1 2 3 J12 USB 0 1 J13 USB 4 5 J14 USB 2 3 J1...

Page 19: ...n in Figure 2 7 Both jumper headers provide 0 079 2mm pitch Figure 2 7 Jumper Header Locations Top Side Table 2 3 Jumper Settings Jumper Header Installed Removed JP1 Clear CMOS Enable Disable Default JP3 LVDS Voltage Selection Enable 3 3V 1 2 Default Enable 5V 2 3 CM720_Top_Jmpr_a Key JP1 Clear CMOS JP3 LVDS Voltage Select JP3 JP1 ...

Page 20: ...or on the upper board surface This does not include the heatsink which is required on all versions of the board but does not increase the height of the board Component height should not exceed 0 345 8 763mm from the upper surface of the board and 0 190 4 826mm from the lower surface of the board See Figure 2 9 on page 17 for the stack height of the heatsink on the board Weight 0 12 kg 0 25 lbs Hei...

Page 21: ...s on headers and connectors represent pin 1 Black square pins on right angle headers represent pin 2 in top side views and pin 1 in bottom side views CM720_Top_Dmn_a 0 00 0 00 0 20 5 08mm 0 50 12 70mm 1 38 35 05mm 3 35 85 09mm 3 55 90 17mm 4 05 102 87mm 3 55 90 17mm 3 20 81 28mm 0 30 7 62mm 0 50 12 70mm 0 20 5 08mm 0 33 8 38mm 1 95 49 53mm 3 45 87 63mm 3 58 90 93mm 3 78 96 01mm 0 00 ...

Page 22: ... provides the most efficient operating and storage condition ranges required for this module Table 2 5 Power Supply Requirements Parameter 600MHz E620T Characteristics 1 3GHz E660T Characteristics 1 6GHz E680T Characteristics Input Type Regulated DC voltages Regulated DC voltages Regulated DC voltages Typical In rush Current Peak 16 24A 81 20W 16 24A 81 20W 16 24A 81 20W Typical Idle Current 1 67A...

Page 23: ...ce of heat on the board The CoreModule 720 is designed to operate at the maximum speed of the CPU and requires a heatsink provided See Figure 2 9 for height measurements of the board and heatsink assembly Figure 2 9 Stack Height of Cooling Assembly NOTE All heights are given in inches 0 39 0 44 Heatsink CoreModule 720 ...

Page 24: ...Chapter 2 Product Overview 18 Reference Manual CoreModule 720 ...

Page 25: ...ess Map Serial Port Interfaces USB Interfaces Ethernet Interface Video Interfaces LVDS SDVO Power Interface GPIO Interface Utility Interface Power Button Reset Switch Speaker SMBus Interface CAN Controller Area Network Interface I2 C Interface System Fan Interface Battery Interface Ethernet LED Interface Miscellaneous SSD SATA Solid State Drive Time of Day RTC Oops Jumper BIOS Recovery Serial Cons...

Page 26: ...he CoreModule 720 employs two ranks of four system DRAM memory chips which provide up to 2GB of extended memory supporting aggressive power management to reduce power consumption shallow self refresh and a new deep self refresh proactive page closing policies to close unused pages and partial writes through data mask pins NOTE ADLINK Technology Inc only supports the features and options listed in ...

Page 27: ...ath Coprocessor X PCI INTA Automatically Assigned PCI INTB Automatically Assigned PCI INTC Automatically Assigned PCI INTD Automatically Assigned USB Automatically Assigned Video Automatically Assigned NOTE The IRQs for USB and Video are automatically assigned by the BIOS Plug and Play logic Local IRQs assigned during initialization can not be used by external devices Table 3 2 Memory Map Base Add...

Page 28: ...Clock 0080 009F DMA Page Registers 00A0 00BF Slave Interrupt Controller 00C0 00DF Slave DMA Controller 2 00F0 00FF Math Coprocessor 02E8 02EF Serial Port 4 COM3 02F8 02FF Serial Port 2 COM1 03B0 03BB Video monochrome 03C0 03DF VGA 03E8 03EF Serial Port 3 COM2 03F8 03FF Serial Port 1 COM0 0400 041F SMBus Configuration Ports 0500 053F PCH GPIO Configuration Ports 0800 087F PCH Power Management Ports...

Page 29: ...ents this input is driven by DTR as part of the DTR DSR handshake 2 S0_DSR 6 COM0 Data Set Ready Indicates external serial device is powered initialized and ready Used as hardware handshake with DTR for overall readiness 3 S0_RXD 2 COM0 Receive Data Serial port receive data input is typically held at a logic 1 mark when no data is being transmitted and is held Off for a brief interval after an On ...

Page 30: ...ive data input is typically held at a logic 1 mark when no data is being transmitted 3 GND 5 Ground 4 S2_TXD 3 COM2 Transmit Data Serial port transmit data output is typically held to a logic 1 when no data is being sent 5 S2_RXD 2 COM2 Receive Data Serial port receive data input is typically held at a logic 1 mark when no data is being transmitted 6 GND 5 Ground 7 S3_TXD 3 COM3 Transmit Data Seri...

Page 31: ...USB3 Power VCC 5V 5 power goes to the port through an on board fuse Port is disabled if this input is low 3 CONN_USB2_N USB2 Port Data Negative 4 CONN_USB3_N USB3 Port Data Negative 5 CONN_USB2_P USB2 Port Data Positive 6 CONN_USB3_P USB3 Port Data Positive 7 USB_GND2 USB2 Ground 8 USB_GND3 USB3 Ground 9 USB_GND2 USB2 Ground 10 USB_GND3 USB3 Ground Table 3 8 USB4 and USB5 Interface Pin Signals J13...

Page 32: ...nce is enhanced by a proprietary collision reduction mechanism IEEE 802 3 compatible physical layer to wire transformer IEEE 802 3u Auto Negotiation support Fast back to back transmission support with minimum interframe spacing IFS IEEE 802 3x auto negotiation support for speed and duplex operation On board magnetics Ethernet isolation transformer Table 3 9 describes the pin signals of the Etherne...

Page 33: ...ovides a control bus able to operate at up to 1 MHz LVDS Supports a maximum resolution of 1280 x 768 at 60Hz pixel clock rate up to 80MHz Supports minimum pixel clock rate of 19 75MHz Supports a single channel interface through a 20 pin header Supports pixel color depths of 18 and 24 bits Supports 20MHz to 80MHz derivative clock frequency Table 3 10 lists the pin signals of the SDVO FPC connector ...

Page 34: ...2 Table 3 11 LVDS Video Interface Pin Signals J23 Pin Signal Description 1 12V 12 volts for flat panel and backlight 2 VCC_LVDS_CONN JP3 determines LVDS voltage 3 3V or 5V 3 GND Ground 4 GND Ground 5 LVDSA_CLK_P LVDS A Clock Positive 6 LVDSA_CLK_N LVDS A Clock Negative 7 LVDSA_DAT3_P LVDS A DATA Positive Line 3 8 LVDSA_DAT3_N LVDS A DATA Negative Line 3 9 LVDSA_DAT2_P LVDS A DATA Positive Line 2 1...

Page 35: ...example applications refer to the GPIO Readme in each BSP directory of the QuickDrive For more information about the GPIO pin operation refer to the PCH EG20T datasheet at http download intel com embedded chipsets datasheet 324211 pdf Table 3 13 describes the pin signals of the GPIO interface which consists of a 10 pin header with 2 rows odd even pin sequence 1 2 and 0 079 2mm pitch Note The shade...

Page 36: ...the Power Button for one second to power on the system Reset Switch Pins 2 and 3 on the Utility header provide the signal for an external reset button which allows the user to re boot the system Speaker The speaker signal provides sufficient signal strength to drive an external 1W 8 Ω Beep speaker at an audible level through pins 4 and 5 on the Utility header The speaker signal is driven from an o...

Page 37: ...nd receives CAN signals to and from the CAN header J4 The CAN interface delivers CAN signals used for automotive industrial automation and medical scanning and imaging applications The following list describes some of the features of the CAN Bus Interface 12 kV ESD protection Low current Standby mode with bus wake up 5 A typical Bus fault protection of 27V to 40V Over temperature shutdown Table 3 ...

Page 38: ...14 defines the pin signals of the I2C bus interface which provides a 5 pin single row header with 0 079 2mm pitch Note The shaded table cells denote power or ground System Fan Table 3 19 lists the pin signals of the System Fan header which provides a single row of 3 pins with 0 079 2mm pitch Note The shaded table cells denote power or ground Battery Table 3 20 lists the pin signals of the External...

Page 39: ...ng you to boot using default settings Use a jumper to connect the DTR pin 4 to the RI pin 9 on Serial Port 1 COM0 prior to boot up to prevent the present BIOS settings from loading After booting with the Oops jumper in place remove the Oops jumper and return to BIOS Setup You must now load factory defaults by selecting Restore Defaults from the Save Exit menu Then select Save Changes and Exit to r...

Page 40: ...atchdog Timer can be used both during the boot process and during normal system operation During the Boot process If the operating system fails to boot in the time interval set in the BIOS the system will reset Enable the WDT using Watchdog Timer of the Boot menu in BIOS Setup Set the WDT for a time out interval in seconds between 0 and 600 in one second increments in the Boot Configuration screen...

Page 41: ...OS setup through a remote serial terminal or PC 1 Turn on the power supply to the CoreModule 720 and enter the BIOS Setup Utility using a local video display 2 Ensure the BIOS feature Serial Port Console Redirection is set to Enabled under the Advanced menu 3 Accept the default options or make your own selections for the balance of the Console Redirection fields and record your settings 4 Ensure y...

Page 42: ... can be a company logo or any custom image the user wants to display during the boot process The custom image can be displayed as the first image on screen during the boot process and remain there while the OS boots depending on the options selected in BIOS Setup Logo Image Requirements Please contact your ADLINK Sales Representative for more information on OEM Logo Utility requirements NOTE The s...

Page 43: ...ime Advanced Launch PXE OpROM Launch Storage OpROM PCI Subsystem CPU GPIO Thermal SDIO USB Hardware Monitor Serial Port Console Chipset North Bridge and South Bridge configurations Boot Boot up Settings Boot Options Boot Order Security Setting or changing Passwords Save Exit Exiting with or without changing settings loading and restoring Optimal or User Defaults Aptio Setup Utility Copyright C 20X...

Page 44: ... Priority 64 PCI Bus Clock EFI Compatible ROM PCI Common Settings PCI Latency Timer 32 PCI Bus Clocks 64 PCI Bus Clocks 96 PCI Bus Clocks 128 PCI Bus Clocks 160 PCI Bus Clocks 192 PCI Bus Clocks 224 PCI Bus Clocks 248 PCI Bus Clocks Aptio Setup Utility Copyright C 20XX American Megatrends Inc Legacy OpROM Support Version X XX XXXX Copyright C 20XX American Megatrends Inc CM720_BIOS_Advanced_a Main...

Page 45: ... Force L0 WARNING Enabling ASPM may cause some PCI E devices to fail Extended Synch Disabled Enabled CPU Configuration Processor Type Genuine Intel R CPU EMT64 Supported Processor Speed XXXX MHz Ratio Status XX Actual Ratio XX System Bus Speed XXX MHz Processor Stepping XXXXX Microcode Revision XXX L1 Cache RAM XX k L2 Cache RAM XXX k Processor Core Single Hyper Threading Supported Intel SpeedStep...

Page 46: ... C 70 C 80 C 90 C 95 C 100 C Passive Trip Point Disabled 30 C 40 C 50 C 60 C 70 C 80 C 90 C 95 C 100 C Passive TC1 Value 1 Passive TC2 Value 5 Passive TSP Value 10 Thermal Offset Disabled Enabled DTS Calibration Disabled Enabled SDIO Configuration SDIO Access Mode Auto DMA PIO USB Configuration USB Devices 1 Keyboard Legacy USB Support Disabled Enabled EHCI Hand off Disabled Enabled USB hardware d...

Page 47: ... Configuration Memory Information MRC Version XX XX Total Memory XXXX MB DDR2 NOTE The serial port console is not hardware protected Diagnostic software that probes hardware addresses may cause a loss or failure of the serial console functions Aptio Setup Utility Copyright C 20XX American Megatrends Inc Version X XX XXXX Copyright C 20XX American Megatrends Inc CM720_BIOS_Chipset_a Main Advanced C...

Page 48: ...Boot Display Configuration Boot Display Device Integrated LVDS External DVI HDMI Flat Panel Scaling Auto Forced Disabled Flat Panel Type 640x480 18bit 800x600 18bit 1024x600 18bit 1024x768 18bit 1280x768 18bit 640x480 24bit 800x600 24bit 1024x600 24bit 1024x768 24bit 1280x768 24bit South Bridge Chipset Configuration SMBUS Controller Enabled Disabled High Precision Event Timer Configuration High Pr...

Page 49: ...led Hard Drive BBS Priorities Boot Option 1 P1 GLS85LS1032A CS 32GBN A101C0 Disabled Aptio Setup Utility Copyright C 20XX Amreican Megatrends Inc Boot Configuration Boot Option Priorities CSM16 Module Version XX XX Version X XX XXXX Copyright C 20XX American Megatrends Inc CM720_BIOS_Boot_a Main Advanced Chipset Boot Security Save Exit Quiet Boot Enabled Fast Boot Disabled Setup Prompt Timeout 1 B...

Page 50: ...n this only limits access to Setup and is only asked for when entering Setup If ONLY the User s password is set then this is a power on password and must be entered to boot or enter Setup In Setup the User will have Administrator rights Version X XX XXXX Copyright C 20XX American Megatrends Inc CM720_BIOS_Security_a Main Advanced Chipset Boot Security Save Exit Administrator Password User Password...

Page 51: ...Load Previous Values Yes No Restore Defaults Load Optimized Defaults Yes No Aptio Setup Utility Copyright C 20XX American Megatrends Inc Version X XX XXXX Copyright C 20XX American Megatrends Inc CM720_BIOS_Save Exit_a Main Advanced Chipset Boot Security Save Exit Save Changes and Exit Save Changes and Reset Discard Changes and Exit Discard Changes and Reset Save Options Boot Override Save Changes...

Page 52: ...ser Defaults Save configuration Yes No Restore User Defaults Restore User Defaults Yes No Boot Override P1 GLS85LS1032A CS 32GBN A101C0 Save configuration and reset Yes No Built in EFI Shell NOTE Selecting this setting enters the system into the EFI Shell mode screen ...

Page 53: ...and then going to the Ask a Question feature Requests can be submitted 24 hours a day 7 days a week You will receive immediate confirmation that your request has been entered Once you have submitted your request you must log in to go to My Stuff area where you can check status update your request and access other features Download Service This service is also free and available 24 hours a day at h...

Page 54: ...aison Office Address 15 rue Emile Baudot 91300 Massy CEDEX France Tel 33 0 1 60 12 35 66 Fax 33 0 1 60 12 35 66 Email france adlinktech com ADLINK Technology Japan Corporation Address ͱ101 0045 ᵅҀ䛑गҷ ऎ 䤯 ފ 3 7 4 374 ɛɳ 4F KANDA374 Bldg 4F 3 7 4 Kanda Kajicho Chiyoda ku Tokyo 101 0045 Japan Tel 81 3 4455 3722 Fax 81 3 5209 6013 Email japan adlinktech com ADLINK Technology Inc Korean Liaison Office ...

Page 55: ...t 21 J jumper locations 13 L low voltage limit 29 LVDS voltage 13 M major integrated circuits 8 mechanical dimensions 15 MiniModules 3 O Oops jumper BIOS recovery 33 P PC 104 Architecture 3 pin sequence 12 power interface 29 requirements 16 power interface 29 product description 4 R Real Time Clock RTC 33 references CAN specification 1 I2C specification 1 LPC specification 1 PC 104 specification 1...

Page 56: ... 24 user GPIO signals 29 Utility header 30 video 6 Watchdog Timer 6 System fan interface 32 T Technical Support 47 thermal cooling processor requirements 17 thickness 14 U USB ports 24 Utility header external speaker connection 30 reset switch connection 30 V voltage requirements 29 W Watchdog Timer WDT 34 web sites 1 weight 14 ...

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