ADLINK Technology COM Express cExpress-BL User Manual Download

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Page 46

6.5.

PCI Configuration Space Map

Bus

Number

Device

Number

Function

Number

Routing

Description

00h

N/A

Intel host Bridge

00h 02h 00h Internal Intel

I.G.D

00h

03h

00h

Internal

HD Audio Device

00h

13h

00h

Internal

Instel Smart Sound Technology Controller

00h 14h 00h Internal xHCI

Controller

00h

15h

00h

Internal

Intel Serial I/O DMA Controller

00h

15h

01h

Internal

Intel Serial I/O I2C Controller #0

00h

15h

02h

Internal

Intel Serial I/O I2C Controller #1

00h

15h

03h

Internal

Intel Serial I/O GSPI Controller #0

00h

15h

04h

Internal

Intel Serial I/O GSPI Controller #1

00h

15h

05h

Internal

Intel Serial I/O UART Controller #0

00h

15h

06h

Internal

Intel Serial I/O UART Controller #1

00h

16h

00h

Internal

Intel Management Engine Interface #1

00h

16h

01h

Internal

Intel Management Engine Interface #2

00h 17h 00h Internal SDIO

Controller

00h

19h

00h

Internal

Gigabit Etherent Controller

00h

1Bh

00h

Internal

High Definition Audio controller

00h

1Ch

00h

Internal

Intel PCI Express Root port 1

00h

1Ch

01h

Internal

Intel PCI Express Root port 2

00h

1Ch

02h

Internal

Intel PCI Express Root port 3

00h

1Ch

03h

Internal

Intel PCI Express Root port 4

00h

1Ch

04h

Internal

Intel PCI Express Root port 5

00h

1Ch

05h

Internal

Intel PCI Express Root port 6

00h

1Dh

00h

Internal

Intel USB EHCI Controller #1

00h

1Fh

00h

N/A

Intel LPC Interface Bridge

00h

1Fh

02h

Internal

SATA Host Controller #1

00h 1Fh 03h Internal SMBus

Controller

00h 1Fh 06h Internal Thermal

Controller

Summary of Contents for COM Express cExpress-BL

Page 1: ...Leading EDGE COMPUTING cExpress BL User s Manual Manual Revision 1 2 Revision Date January 2 2018 Part Number 50 1J061 1020...

Page 2: ...1 00 Initial release 2015 05 07 JC 1 01 Update CPU COM port power mgmt specifications correct LVDS pinout correct audio LVDS eDP GbE SATA SPI Fan SMBus DDI signal descriptions update BIOS setup 2015...

Page 3: ...ven if advised of the possibility of such damages Environmental Responsibility ADLINK is committed to fulfill its social responsibility to global environmental preservation through compliance with the...

Page 4: ...ating Temperatures 9 2 13 Environmental 9 2 14 Specification Compliance 9 2 15 Operating Systems 9 2 16 Functional Diagram 10 2 17 Mechanical Drawing 11 3 Pinouts and Signal Descriptions 12 3 1 AB CD...

Page 5: ...6 PCI Interrupt Routing Map 47 6 7 SMBus Address Table 47 7 BIOS Setup 48 7 1 Menu Structure 48 7 2 Main 49 7 3 Advanced 53 7 4 Boot 69 7 5 Security 70 7 6 Save Exit 70 8 BIOS Checkpoints Beep Codes...

Page 6: ...MM sockets to provide excellent overall performance Integrated Intel Generation 8 Graphics includes features such as OpenGL 4 2 DirectX 11 1 Intel Clear Video HD Technology Advanced Scheduler 2 0 1 0...

Page 7: ...up in 8MB SPI BIOS with Intel AMT 10 0 support AMT supported on i7 i5 SKUs only 2 2 Expansion Busses 4x PCI Express x1 AB Lanes 0 1 2 3 LPC bus SMBus system I2C user 2 3 Video Integrated on Processor...

Page 8: ...OS supported during BIOS POST COM Port Description IRQ Address Console redirection support COM 1 Supported by module SER0 A98 A99 via NCT5104D 10 0x240 Yes COM 2 Supported by module SER1 A101 A102 via...

Page 9: ...5 for 5Vsb power saving 2 12 Operating Temperatures Standard Operating Temperature 0 C to 60 C Wide Voltage Input Extreme Rugged Operating Temperature optional 40 C to 85 C Standard Voltage Input 2 13...

Page 10: ...Page 10 2 16 Functional Diagram...

Page 11: ...cExpress BL Page 11 2 17 Mechanical Drawing Top View Side View All tolerances 0 05 mm Other tolerances 0 2 mm connectors on bottom side Dimensions mm...

Page 12: ...SMB_CK C13 USB_SSRX3 D13 USB_SSTX3 A14 GBE0_CTREF B14 SMB_DAT C14 GND D14 GND A15 SUS_S3 B15 SMB_ALERT C15 DDI1_PAIR6 D15 DDI1_CTRLCLK_AUX A16 SATA0_TX B16 SATA1_TX C16 DDI1_PAIR6 D16 DDI1_CTRLDATA_AU...

Page 13: ...ANE_RV A55 PCIE_TX4 B55 PCIE_RX4 C55 PEG_RX1 D55 PEG_TX1 A56 PCIE_TX4 B56 PCIE_RX4 C56 PEG_RX1 D56 PEG_TX1 A57 GND B57 GPO2 C57 TYPE1 D57 TYPE2 A58 PCIE_TX3 B58 PCIE_RX3 C58 PEG_RX2 D58 PEG_TX2 A59 PC...

Page 14: ...RX12 D92 PEG_TX12 A93 GPO0 B93 VGA_HSYNC C93 GND D93 GND A94 SPI_CLK B94 VGA_VSYNC C94 PEG_RX13 D94 PEG_TX13 A95 SPI_MOSI B95 VGA_I2C_CK C95 PEG_RX13 D95 PEG_TX13 A96 TPM_PP B96 VGA_I2C_DAT C96 GND D9...

Page 15: ...tput 5V signal level I O 3 3V Bi directional signal 3 3V tolerant I O 5V Bi directional signal 5V tolerant I O 3 3Vsb Input 3 3V tolerant active in standby state P Power Input Output REF Reference vol...

Page 16: ...B28 support on this platform 3 3 2 Analog VGA Signal Pin Description I O PU PD Comment VGA_RED B89 Red for monitor Analog DAC output designed to drive a 37 5 Ohm equivalent load O Analog Not supported...

Page 17: ...S_BKLT_CTRL B83 LVDS panel backlight brightness control O 3 3V ePD to LVDS requirement LVDS_I2C_CK A83 DDC lines used for flat panel detection and control O 3 3V PU 2k2 3 3V LVDS_I2C_DAT A84 DDC lines...

Page 18: ...ay be as low as 0V and as high as 3 3V The reference voltage output shall be current limited on the Module In the case in which the reference is shorted to ground the current shall be 250 mA or less G...

Page 19: ...dule PCIE_TX4 PCIE_TX4 A55 A56 PCI Express channel 4 Transmit Output differential pair O PCIE PCIe port 4 is Connected to LAN PCIE_RX4 PCIE_RX4 B55 B56 PCI Express channel 4 Receive Input differential...

Page 20: ...ver current sense USB ports 0 and 1 A pull up for this line shall be present on the module An open drain driver from a USB current monitor on the carrier board may drive this line low I 3 3VSB PU 10k...

Page 21: ...odule to carrier board SPI BIOS flash O 3 3VSB SPI_POWER A91 Power supply for Carrier Board SPI sourced from Module nominally 3 3V The Module shall provide a minimum of 100mA on SPI_POWER Carriers sha...

Page 22: ...Description I O PU PD Comment SMB_CK B13 System Management Bus bidirectional clock line Power sourced through 5V standby rail and main power rails I O OD 3 3VSB PU 8k2 3 3VSB SMB_DAT B14 System Manage...

Page 23: ...ive low request for module to reset and reboot May be falling edge sensitive For situations when SYS_RESET is not able to reestablish control of the system PWR_OK or a power cycle may be used I 3 3VSB...

Page 24: ...U 10K 3 3VSB Emulated on GPIO BIOS 3 3 18 Power and Ground Signal Pin Description I O PU PD Comment VCC_12V A104 A109 B104 B109 Primary power input 12V nominal 5 20V wide input All available VCC_12V p...

Page 25: ...d USB data path on USB2 I PCIE Not supported USB_SSTX2 USB_SSTX2 D9 D10 Additional Transmit signal differential pairs for the SuperSpeed USB data path on USB2 O PCIE Not supported USB_SSRX3 USB_SSRX3...

Page 26: ...erface Hot Plug Detect I PCIE PD 10M IF DDI1_DDC_AUX_SEL is floating I O PCIe DP1_AUX DDI1_CTRLCLK_AUX D15 IF DDI1_DDC_AUX_SEL pulled high I O OD 3 3V HDMI1_CTRLCLK IF DDI1_DDC_AUX_SEL is floating I O...

Page 27: ...UX signals If pulled high the AUX pair contains the CRTLCLK and CTRLDATA signals PD 1M DDI 3 Signal Pin Description I O PU PD Comment DDI3_PAIR0 DDI3_PAIR0 DDI3_PAIR1 DDI3_PAIR1 DDI3_PAIR2 DDI3_PAIR2...

Page 28: ...I1_PAIR5 Not supported Not supported C15 DDI1_PAIR6 Not supported Not supported C16 DDI1_PAIR6 Not supported Not supported C24 DDI1_HPD DP1_HPD HDMI1_HPD D15 DDI1_CTRLCLK_AUX DP1_AUX HMDI1_CTRLCLK D16...

Page 29: ...66 C68 C69 C71 C72 C74 C75 C78 C79 C81 C82 C85 C86 C88 C89 C91 C92 C94 C95 C98 C99 C101 C102 PCI Express Graphics transmit differential pairs I PCIE Not supported PEG_TX0 PEG_TX0 PEG_TX1 PEG_TX1 PEG_T...

Page 30: ...Type 5 no IDE no PCI GND NC NC Pinout Type 6 no IDE no PCI The Carrier Board should implement combinatorial logic that monitors the module TYPE pins and keeps power off e g deactivates the ATX_ON sign...

Page 31: ...tors and pinouts LEDs and switches that are used on the module but are not included in the PICMG standard specification Connector and LED Locations CD AB FAN L E D 1 4 pin Fan 40 pin Debug Connector B...

Page 32: ...Page 32 4 1 40 pin Debug Connector FPC Connector Type FCI 59GF Flex 10042867 Pin Orientation cExpress BL and the DB40 Debug Module...

Page 33: ...MC Program interface continued OCD0B Include a jumper to connect OCD0A via 1K0 pull up to 3 3V_BMC 9 GND 29 PWRBTN 10 BIOS_DIS0 30 SYS_RESET 11 RST 31 CB_RESET 12 CLK33_LPC 32 CB_PWROK 13 LPC_FRAME 33...

Page 34: ...D2 Green Power Source 3Vcc S0 LED ON S3 S4 S5 LED OFF ECO mode LED OFF LED3 Red BMC output and same signal as WDT B27 on BtB connector Module power up WD LED LED OFF Watchdog counting WD LED LED OFF W...

Page 35: ...CFG 4 2 I O Processor 28 OBSDATA_D0 CFG 12 2 I Processor 29 OBSDATA_B1 CFG 5 2 I O Processor 30 OBSDATA_D1 CFG 13 2 I Processor 31 GND GND NA 32 GND GND NA 33 OBSDATA_B2 CFG 6 2 I O Processor 34 OBSD...

Page 36: ...aults Reset Button To perform a hardware reset of BIOS default settings perform the following steps 1 Shut down the system 2 Press the BIOS Setup Defaults RESET Button continuously and boot up the sys...

Page 37: ...Failsafe mode both BIOS chips on the module are configured as SPI1 Only one of the two is connected to the SPI bus at any given time In case of failure of the primary SPI1 BIOS the system will reboot...

Page 38: ...cycles counter Boot counter Counts the number of boot attempts Watchdog Timer Type II Set Reset Disable Watchdog Timer Features auto reload at power up System Restart Cause Power loss BIOS Fail Watchd...

Page 39: ...ENT Use Main Current Function 5 1 2 Main Current The BMC of the cExpress BL implements a current monitor The current can be read by calling the SEMA function Get Main Current The function returns four...

Page 40: ...eded or supported Exception Code Error Message 0 NOERROR 2 NO_SUSCLK 3 NO_SLP_S5 4 NO_SLP_S4 5 NO_SLP_S3 6 BIOS_FAIL 7 RESET_FAIL 8 POWER_FAIL 9 LOW_VIN 11 VCORE 12 P1V05_S 13 P3V3_A 14 VDDQ 15 P5V_A...

Page 41: ...4GB 20MB 4GB 19MB 1 FEC00000 FECFFFFF 1 MB APIC Configuration Space 15MB 16MB F00000 FFFFFF 1 MB ISA Hole 1MB 15MB 100000 EFFFFF 14MB Main Memory 0K 1MB 00000 FFFFFF 1MB DOS Compatibility Memory 6 2...

Page 42: ...Reset Bit 0 Fast Gate A20 Bit 1 091 93 9F Reserved 0A0 0B1 and 0B4 0BF Interrupt controller 2 8259 equivalent 0B2 and 0B3 APM control and status port respectively 0C0 0DF Reserved 0E0 0EF Available 0...

Page 43: ...igger register CF8 CFB PCI configuration address register 32 bit I O only CF9 Reset Control register 8 bit I O CFC CFF PCI configuration data register F040 Smbus base address for SB 1C00 GPIO Base Add...

Page 44: ...Q10 via SERIRQ PIRQ Note 1 11 Serial Port 4 COM4 IRQ11 via SERIRQ PIRQ Note 1 12 PS 2 Mouse IRQ12 via SERIRQ PIRQ Note 1 13 GSPI UART I2C SDIO N A Note 1 14 gpio PIRQ Note 1 15 gpio PIRQ Note 1 Note 1...

Page 45: ...ERIRQ PIRQ Note 1 16 N A P E G Root Port Intel HDA PCIE Port 0 1 2 3 4 5 6 EHCI Conterller 2 I G D XHCI Controller Note 1 17 N A PCIE Port 0 1 2 3 4 5 6 P E G Root Port Note 1 18 N A PCIE Port 0 1 2 3...

Page 46: ...0 00h 15h 06h Internal Intel Serial I O UART Controller 1 00h 16h 00h Internal Intel Management Engine Interface 1 00h 16h 01h Internal Intel Management Engine Interface 2 00h 17h 00h Internal SDIO C...

Page 47: ...NTA 16 INTB 17 INTC 18 INTD 19 INTA 16 INTB 17 INTH 23 INTA 16 Int1 INTB 17 INTC 18 INTD 19 INTA 16 INTB 17 INTC 18 INTD 19 INTF 21 Int2 INTC 18 INTD 19 INTA 16 INTB 17 INTC 18 INTD 19 INTA 16 INTC 18...

Page 48: ...unction of each setting is described in the right hand column of the respective table Main Advanced Security Boot Save Exit System Information Processor Information VGA Firmware Version Memory Informa...

Page 49: ...U Brand String Info only Display CPU Brand Name Frequency Info only Display CPU Frequency Number of Processors Info only Display number of Processors GT Info Info only Display GT info of Intel Graphic...

Page 50: ...Info only Current Read only Display CPU current temperature Startup Read only Display CPU startup temperature Min Read only Display CPU min temperature Max Read only Display CPU max temperature Board...

Page 51: ...down Boot Cycles Read only The Bootcounter is increased after a HW or SW Reset or after a successful power up Boot Reason Read only The boot reason is the event which causes the reboot of the system 1...

Page 52: ...e 60 Specifies the temperature threshold at which the BMC turnn on CPU fan with specific PWM level PWM Level 40 Select PWM level CPU Trigger Point 3 Read only Trigger Temperature 70 Specifies the temp...

Page 53: ...nfo L2 Cache Info only Display cache info L3 Cache Inf o only Display cache info Limit CPUID Maximum Disabled Enabled When Enabled the processor will limit the maximum CPUID input value to 03h when qu...

Page 54: ...y tCL Info only Display CAS Latency tCL Minimum delay time Info only Display Minimum delay time CAS to RAS tRCDmin Info only Display CAS to RAS tRCDmin Row Precharge tRPmin Info only Display Row Prech...

Page 55: ...abled based on the setup options Aperture Size 128MB 256MB 512MB Select the Aperture Size DVMT Pre Allocated XXM Select DVMT 5 0 Pre Allocated Fixed Graphics Memory size used by the Internal Graphics...

Page 56: ...by the Internal Graphics Device GT Power Management Control Info only GT Info Info only Display GT info of Intel Graphics RC6 Render Standby Enabled Disabled Check to enable render standby support GT...

Page 57: ...TA Enabled Disabled If enabled then only IRRT volumes can span internal and eSATA drives If disabled then any RAID volume can span internal and eSATA drives Smart Response Technology Enabled Disabled...

Page 58: ...time out value for Control Bulk and Interrupt transfers Device reset time out 10 sec 20 sec 30 sec 40 sec USB mass storage device Start Unit command time out Device power up delay Auto Manual Maximum...

Page 59: ...nabled Disabled Un Configure ME without password Amt Wait Timer 0 Set timer to wait before sending ASF_GET_BOOT_OPTIONS Disable ME Enabled Disabled Set ME to Soft Temporary Disabled ASF Enabled Disabl...

Page 60: ...evice or allow System BIOS to select the value ASPM Support Warning Enabling ASPM may cause some PCI E devices to fail Disable Auto Force L0S Set the ASPM Level Force L0s Force all links to L0s State...

Page 61: ...Port 4 x1 2x2 Port 1 2 x2 and Port 3 4 x2 1x4 Port 1 x4 Ports 2 4 disable PCI Express Root Port 1 4 Submenu Configure PCI Express Root Port 1 4 setting PCIE Port 5 is assigned to LAN Info only Advance...

Page 62: ...chable Memory Range for this Root Bridge Reserved I O 4 Reserved I O 4K 8K 12K 16K 48K Range for this Root Bridge PCIE LTR Disable Enable PCIE Latency Reporting Enable Disable PCIE LTR Lock Disable En...

Page 63: ...ation Info only Serial Port 1 Configuration Serial Port Device Settings Change Settings Device Mode Enabled Disabled IO 240h IRQ 10 Auto IO 240h IRQ 10 IO 240h IRQ 10 11 12 IO 248h IRQ 10 11 12 IO 250...

Page 64: ...USPEND button is pressed 7 3 10 Advanced Sound Feature Options Description Sound Info only Azalia Disable Enable Auto Control Detection of the Azalia device Disabled Azalia will be unconditionally dis...

Page 65: ...Space Select Parity Stop Bits 1 2 Select number of stop bits Flow Control None Hardware RTS CTS Select flow control VT UTF8 Combo Key Support Disable Enable Enable VT UTF8 Combination Key Support for...

Page 66: ...anges is pressed BCLK DMI PEG PCIe PCI33 SATA USB3 info only Maximum supported frequency info only Minimum supported frequency info only Current frequency info only Supported SSC modes info only Curre...

Page 67: ...trols the temperature of the ACPI Passive Trip Point the point in which the OS will begin throttling the processor Passive TC1 Value 1 This value sets the TC1 value for the ACPI Passive Cooling Formul...

Page 68: ...own BIOS Interface Lock Enabled Disabled Enable or Disable the BIOS interface lockdown RTC RAM Lock Enabled Disabled Enable or Disable bytes 38h 2Fh in the upper and lower 128 byte bank of the RTC RAM...

Page 69: ...n Submenu CSM configuration Enable Disable Option ROM execution settings etc 7 4 2 Boot CSM Configuration Feature Options Description CSM Support Enable Disable Enable Disable CSM Support CSM16 Module...

Page 70: ...system Save Changes and Reset Discard Changes and Reset Reset the system without saving any changes Discard Changes and Reset 7 6 2 Save and Exit Save Options Feature Options Description Save Changes...

Page 71: ...el Platform Innovation Framework for EFI the Framework The Framework refers the following boot phases which may apply to various status code checkpoint descriptions Security SEC initial low level init...

Page 72: ...s PEI 8 2 Standard Status Codes 8 2 1 SEC Phase Status Code Description 0x00 Not used Progress Codes 0x01 Power on Reset type detection soft hard 0x02 AP initialization before microcode loading 0x03 N...

Page 73: ...cific 0x19 Pre memory South Bridge initialization is started 0x1A Pre memory South Bridge initialization South Bridge module specific 0x1B Pre memory South Bridge initialization South Bridge module sp...

Page 74: ...Codes 0x50 Memory initialization error Invalid memory type or incompatible memory speed 0x51 Memory initialization error SPD reading has failed 0x52 Memory initialization error Invalid memory size or...

Page 75: ...capsule is not found 0xFA Invalid recovery capsule 0xFB 0xFF Reserved for future AMI error codes 8 2 4 PEI Beep Codes of Beeps Description 1 Memory not Installed 1 Memory was installed twice InstallP...

Page 76: ...devices initialization 0x73 South Bridge DXE Initialization South Bridge module specific 0x74 South Bridge DXE Initialization South Bridge module specific 0x75 South Bridge DXE Initialization South Br...

Page 77: ...Boot event 0xAE Legacy Boot event 0xAF Exit Boot Services event 0xB0 Runtime Set Virtual Address MAP Begin 0xB1 Runtime Set Virtual Address MAP End 0xB2 Legacy Option ROM Initialization 0xB3 System R...

Page 78: ...sh update is failed 7 Reset protocol is not available 8 Platform PCI resource requirements cannot be met 8 2 7 ACPI ASL Checkpoint Status Code Description 0x01 System is entering S1 sleep state 0x02 S...

Page 79: ...0x05 OEM SEC initialization before microcode loading 0x0A OEM SEC initialization after microcode loading 0x1D 0x2A OEM pre memory initialization codes 0x3F 0x4E OEM PEI post memory initialization code...

Page 80: ...tor with 0 5mm for a stacking height of 5 mm This connector can be used with 5 mm through hole standoffs SMT type Tyco 3 6318491 6 Foxconn QT002206 4141 3H 220 pin board to board connector with 0 5mm...

Page 81: ...2 2 Heat Sinks A heat sink can be used as a thermal solution for a specific COM Express module and can have a fan or be fanless depending on the thermal requirements 9 2 3 Installation Install a heat...

Page 82: ...o the connectors on the carrier board as shown Then press down on the module until it is firmly seated on the carrier board Step 6 Use the five M2 5 L 16mm screws provided to secure the COM Express mo...

Page 83: ...ition to the choice of 5 mm or 8mm board to board connectors there is the choice of Top and Bottom mounting In Top mounting the threaded standoffs are on the carrier board and the thermal solution is...

Page 84: ...ed standoffs are DIP type and through hole standoffs are SMT type Other types not listed are available upon request 5mm through hole standoff SMT type P N 33 72000 0050 5mm threaded standoff DIP type...

Page 85: ...avoid electrical shock and or damage to equipment Keep equipment away from water or liquid sources Keep equipment away from high heat or high humidity Keep equipment properly ventilated do not block o...

Page 86: ...ll Free 1 800 966 5200 USA only Fax 1 408 360 0222 Email info adlinktech com ADLINK Technology China Co Ltd Address 300 Fang Chun Rd Zhangjiang Hi Tech Park Pudong New Area Shanghai 201203 China Tel 8...

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