ADInstruments PowerLab/16SP, Owner'S Manual

Page: 37 / 72

Appendix A — Technical Aspects 29
(analog-to-digital converter). The ADC can sample at up to 200,000
samples per second. The CPU assembles groups of samples into
blocks and then transmits them to the computer, where the
application program receives, records, and displays the data.
Sampled data from the ADC are stored in FIFOs until the CPU is
ready to read them. The FIFOs let the CPU know when they are
getting full, at which point it will read all of their data very quickly.
This frees the CPU from the need to read every sample from the ADC
as it is ready, so that it can perform other tasks.
The external trigger input (marked ‘Trigger’ on the front panel) is
connected to a comparator circuit that triggers when the input
Figure A–2
Block diagram of the
PowerLab/8
SP
50/60Hz
MAINS
SYNC
POWER
SUPPLY
A
A
SCSI PORT USB Port
Ext Trigger
MC68340
CPU
Digital Output Digital Input
I2C Port
LATCH
LATCH
16-BIT ADC
Analog Input Channels
FIFO
RAM
I2C
Controller
ROM
FIFO
Analog Output
DAC
DAC
SCSI
Controller
SYSTEM GLUE
& REAL-TIME
CLOCK
SAMPLING
CONTROL
GLUE
FIFO
LATCH
LATCH
USB
Controller
Multiplexer
Analog Output External Trigger Analog Input