APDCAM User’s Guide
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After the trigger event the data transmission can be delayed by setting the TRIGGER_
DELAY register which allows several ten second delay. After the TRIGGER_DELAY
time data transmission starts and the Trigger Out signal goes to H on the backplate. At
the same time the Data LED shows the active data transmission.
Data from the measurement are continuously filling a ring buffer which size can be set
in register RINGBUFSIZE. This enables a post-trigger capability that is, samples ac-
quired before the trigger event can be transmitted. This is extremely useful when
APDCAM is measuring a fast transient event as the staring phase can be measured with-
out any external trigger.
The timing scheme of a triggered measurement
is shown in Figure 10.
A separate scheme, similar to the internal trigger, is used for overload protection of the
detector. Although it is protected from excess light imput under very unfavourable condi-
tions a long-term overload might cause considerable power dissipation in the detector
which might in turn result in damage. To avoid this an overload protection scheme can
be switched on in the OVERLOAD register. Bits 14 and 15 should be set to 1 to enable
the overload feature and the desired overload level should be entered in bits 0...13. A
typical level would be close to 0 as the detector delivers negative signal. An overload
event is generated when any of the signals fulfills the overload condition for more than
OVERLD_TIME. The overload event switches off the detector bias voltage and lits the
red Overload LED on the backplate. The status of the overload can be read from
OVERLD_STATUS and writing any value into this register clears the overload. The bias
voltage should be switched back in the Control unit. This overload protection works
without the measurement enabled.
3.3.4. Data output format
After a trigger event or stream enable first a preamble block is sent to the output data
stream. This identities the start of the data and contains the stream ID. After that data is
sent in identical sample blocks each containing data from the same sampletime of all the
enabled channels of the given 8-channel ADC block. The data bits are packed bit-
continuously into the sample block and padded to the next full byte. Details are described
in section 3.6.1.
3.3.5. Offset control
The sensitive analog amplifiers or the detector leakage current can cause a drift in the
detector offset voltage. To compensate for this the DAQ unit contains 32 12bit Digital to
Analog Converters (DACs) which can be used to shift the analog input signal to the
ADC. The corresponding values can be entered in the OFFSET register. These values
are 12bit unsigned numbers, increasing values shift the in put signal to higher values. As
the analog amplifiers deliver negative signal the offset should be set close to the upper
limit of the ADCs. Typical needed values are in the 700-900 range.