Adam 821x Manual Download

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Chapter 6 Deployment of the CPU 821xDP

CPU ADAM 821x

6-24

ADAM 8000 Manual CPU 821x – Rev 1.1

Multi master system

More than one master and multiple slaves connected to one bus:

Input/output periphery

CPU 21x DP

Input/output periphery

CPU 21x DP

CPU

IM 208

CPU

IM 208

1,3

IM 253

Input/output periphery

IM 253

Input/output periphery

CPU

IM 208

2,4

IM 253

Input/output periphery

Summary of Contents for 821x

Page 1: ...Subject to change to cater for technical progress Manual ADAM CPU 821x Order No ADAM HB103E Rev 03 04 CPU 821x Revision 1 1...

Page 2: ...ntents of this manual was carefully examined to ensure that it conforms with the described hardware and software However discrepancies can not be avoided The specifications in this manual are examined...

Page 3: ...CPU 821x This chapter describes the deployment of the CPU section together with the peripheral modules of the System 8xxx that are installed on the same bus rail Chapter 4 Deployment of the CPU 821xNE...

Page 4: ...2 14 Technical data 2 15 Chapter 3 Deployment of the CPU 821x 3 1 Start up behavior 3 2 Address allocation 3 3 Preparations required for configuration 3 5 Configuration of directly installed System 82...

Page 5: ...ed standard SFCs 7 4 ADAM specific SFCs 7 6 Include ADAM library 7 7 SFC 220 MMC_CR_F 7 8 SFC 221 MMC_RD_F 7 10 SFC 222 MMC_WR_F 7 11 SFC 223 PWM 7 12 SFC 224 HSC 7 14 SFC 225 HF_PWM 7 16 SFC 227 TD_P...

Page 6: ...ad instructions 8 15 Shift instructions 8 18 Setting resetting bit addresses 8 19 Jump instructions 8 21 Transfer instructions 8 22 Data type conversion instructions 8 25 Comparison instructions 8 26...

Page 7: ...ovides the description of one specific topic This manual provides the following guides An overall table of contents at the beginning of the manual An overview of the topics for every chapter An index...

Page 8: ...s EX zone The manual must be available to all personnel in the project design department installation department commissioning operation The following conditions must be met before using or commission...

Page 9: ...upply 2 9 Project engineering 3 5 Include GSD file 3 5 Requirements 3 5 Project transfer 3 7 5 8 Test functions 3 18 CPU 821xDP 6 1 Cabling 6 21 Commissioning 6 25 Construction 2 4 Diagnostics 6 14 6...

Page 10: ...tion selector RN ST MR 2 9 G Green Cable Hints 1 4 GSD file1 8 3 5 5 4 5 6 6 6 6 8 H H1 4 4 Hardware configurator 1 8 Hardware description 2 1 Hub 4 2 I IND 7 23 Industrial Ethernet 4 4 Instruction li...

Page 11: ...ator word ANZW 7 28 Length word 7 32 Parameter 7 22 Parameter transfer 7 25 Parameterization error PAFE 7 35 RECEIVE SFC 231 7 37 RECEIVE_ALL SFC 237 7 43 RESET SFC 234 7 40 SEND SFC 230 7 36 SEND_ALL...

Page 12: ...spect Below follows a description of Safety information for users Construction and operation of the CPU 821x Programming principles Topic Page Chapter 1 Principles 1 1 Safety information for users 1 2...

Page 13: ...static discharge are usually not detected immediately The respective failure may become apparent after a period of operation Components damaged by electrostatic discharges can fail after a temperature...

Page 14: ...antech you have to make sure that Pin 1 is not connected This may cause transfer problems and in some cases damage the CPU Especially Profibus cables from Siemens like e g the 6XV1 830 1CH30 must not...

Page 15: ...bus masters Via the Green Cable and an upload application you may update the firmware of all recent CPUs 8xxx and certain fieldbus masters see Note Important notes for the deployment of the Green Cabl...

Page 16: ...g picture shows the range of performance of the System82xx System 8000 decentral peripheral Profibus DeviceNet CAN Interbus PC CPU PLC CPU Dig IN Dig OUT Anal IN Anal OUT FM CP DP 8xxx PC 8xxx PLC 8xx...

Page 17: ...4V SM 8221 0 1 2 3 4 5 6 7 ADAM 8221 1BF00 X 2 3 4 1 2 3 4 5 6 7 8 9 I0 DI 8xDC24V SM 8221 0 1 2 3 4 5 6 7 ADAM 8221 1BF00 X 2 3 4 1 2 3 4 5 6 7 8 9 I0 DI 8xDC24V SM 8221 0 1 2 3 4 5 6 7 ADAM 8221 1BF...

Page 18: ...A Inputs 1024Bit E0 0 E127 7 PA Outputs 1024Bit A0 0 A127 7 Order data CPU 21x ADAM 8214 1BA01 ADAM 8215 1BA01 ADAM 8216 1BA01 CPU 21xNET ADAM 8214 2BT01 ADAM 8215 2BT01 ADAM 8216 2BT01 CPU 21xDPM ADA...

Page 19: ...stem 82xx is included to the hardware configurator serial connection to the CPU e g via Green Cable Note The configuration of the CPU requires a thorough knowledge of the Siemens STEP 7 manager and th...

Page 20: ...the CPU is able to recognize the system as central periphery system Add your modules to the slave system in the same order you have assembled them Start with the CPU at plug in location 0 Include your...

Page 21: ...master project engineering Otherwise no Profibus communi cation is possible slave failure Steps of project engineering in the DP master Configure the CPU with DP master system address 2 Add Profibus s...

Page 22: ...sensors and actuators One single CPU may address a maximum of central 32 modules Compact centralized configuration CPU AI 4 AO4 DIO8 DO16 CPU21x DO8 Count Decentralized configuration using Profibus 3...

Page 23: ...tor They support the input output modules and process the data from the function modules Quick programming due to the compatibility with Siemens STEP 7 The compact construction requires less space Enh...

Page 24: ...dentical sequences of operations are repeated in a never ending cycle Where a process requires control signals at constant intervals you can initiate certain operations based upon a timer e g not crit...

Page 25: ...perating modules provide the interfaces to the system routines CPU 821x operands The following operands are available for programming the CPU 821x Process image and periphery Bit memory marker Timers...

Page 26: ...h a value between 10ms and 9990s As soon as the user program executes a start operation the value of this timer is decremented by the interval that you have specified until it reaches zero You may loa...

Page 27: ...lation and commissioning instructions and applications for the memory modules A summary of the integrated FBs and OBs and the technical data conclude the chapter The following section contains descrip...

Page 28: ...he versions 8214 8215 and 8216 Instruction set compatible with Siemens STEP 7 MP Interface for data transfer between PC and CPU Status LEDs for operating mode and diagnostics External memory card MMC...

Page 29: ...ure drivers for different SCADA systems like zenOn InTouch etc Type Order number Description CPU 8214NET ADAM 8214 2BT01 PLC CPU 214 with Ethernet and 32KB of memory CPU 8215NET ADAM 8215 2BT01 PLC CP...

Page 30: ...scription CPU 88214DP ADAM 8214 2BP01 SPS CPU 214 with Profibus slave and 32KB of memory CPU 8215DP ADAM 8215 2BP01 SPS CPU 215 with Profibus slave and 64KB of memory CPU 8216DP ADAM 8216 2BP01 SPS CP...

Page 31: ...CPU 8214DPM ADAM 8214 2BM01 PLC CPU 214 with Profibus DP master and 32kByte memory CPU 8215DPM ADAM 8215 2BM01 PLC CPU 215 with Profibus DP master and 64kByte memory CPU 8216DPM ADAM 8216 2BM01 PLC CP...

Page 32: ...STEP 7 CPU series This series of CPUs provides access to the peripheral modules of the System 82xx You may query sensors and control actuators by means of standardized commands and programs The unit...

Page 33: ...1 MMC 4 5 3 2 1 R S X 2 3 4 ADAM 8216 2BT01 Tx Rx 6 7 M P I 2 IX Data TP Tx Rx 1 RUN STOP OVERALL RESET operating mode selector switch 2 Status indicator LEDs 3 Socket for MMC memory card 4 MP2 I inte...

Page 34: ...7 8 M P I 2 RN IF DE ER D P 2 6 1 RUN STOP OVERALL RESET operating mode selector switch 2 Status indicator LEDs 3 Socket for MMC memory card 4 MP2 I interface 5 Connector for 24V DC power supply 6 Pro...

Page 35: ...of the function selector The CPU automatically executes the operating mode START UP when the mode changes from STOP to RUN You may issue an overall reset by placing the switch in the Memory Reset MR p...

Page 36: ...hould be checked Please contact Advantech The MPI unit provides the link for the data transfer between the CPU and the PC Via bus communication you are able to exchange programs and data between diffe...

Page 37: ...w shows the color and the meaning of these LEDs Name Color Description TxD green Transmit data RxD green Receive data An RJ45 socket provides the interface to the twisted pair cable required for Ether...

Page 38: ...alls below 18V Flashes alternately with RD when the master configuration is bad project configuration error Flashes simultaneously with RD when parameterization is bad RD green On when a data transfer...

Page 39: ...g accessed and the outputs are 0 clear state If both RN DE are on the status of the Master is operate It is communicating with the slaves IF red Initialization error for bad Profibus configurations DE...

Page 40: ...821x Rev 1 1 Block diagram The following block diagram shows the basic hardware construction of the CPU 821x modules Processor System 81xx interface circuitry System 82xx backplane bus Memory Card Tim...

Page 41: ...ber of Blocks FB FC DB 1024 FB0 FB1023 1024 FC0 FC1023 2047 DB1 DB2047 Total addressing space input output 1024 1024Byte each 128 Byte for process image PA PA Inputs 1024Bit E0 0 E127 7 PA Outputs 102...

Page 42: ...ion 500V AC Status indicator LEDs like CPU 821x additionally with LEDs for the Ethernet section Connections interfaces like CPU 821x additionally with RJ45 socket for Twisted Pair Ethernet Ethernet in...

Page 43: ...nector 9pin D type socket Network topology Linear bus active bus termination at both ends Medium Screened and drilled twisted pair cable Depending on environment screening may be omitted Transfer rate...

Page 44: ...nally with 9pin D type socket Profibus Profibus interface Connector 9pin D type socket Network topology Linear bus active bus termination at both ends Medium Screened and drilled twisted pair cable De...

Page 45: ...ins a description of Assembly and commissioning Principle of address allocation Project engineering and parameterization Deployment of MPI and MMC Operating modes and overall reset Usage of test funct...

Page 46: ...SET After delivery the CPU is totally clear After a STOP RUN transition the CPU switches to RUN without application The CPU switches to RUN with the application located in the battery buffered RAM The...

Page 47: ...0 127 are additionally saved in a special memory area called the process image The process image is divided into two parts process image of the inputs PAE process image of the outputs PAA Peripheral a...

Page 48: ...Output byte 1 Output byte 2 Output byte 3 Output byte 127 Output byte 0 Output byte 7 Output byte 8 Output byte 9 Output byte 1023 0 1 2 3 127 128 135 136 137 1023 analog digital PAA 0 1 2 3 127 PAE...

Page 49: ...figuration of the modules The Siemens STEP 7 manager must have been installed The GSD file must have been included in the Siemens hardware configurator A serial connection to the CPU must have been es...

Page 50: ...rt the CPU 315 2DP 6ES7 315 2AF01 0AB0 You have to create a new Profibus subnet Attach the System ADAM_DP8000 to the subnet The respective entries are located in the hardware catalog under PROFIBUS DP...

Page 51: ...ality you may use the ADAM Green Cable to send the data serial by a peer to peer connection The ADAM Green Cable has the OrderNo ADAM 8950 0KB00 and may only be used with ADAM components System 8xxx P...

Page 52: ...CPU parameterization takes place in the parameter dialog of the CPU 315 2DP The parameterization of the Profibus section of the CPU 821xDP takes place via the parameterization dialog of the CPU 821x P...

Page 53: ...hat may be defined in the Siemens STEP 7 manager The following parameters are currently employed by the CPU General MPI address of the CPU maximum MPI address Initialization Start up if the planned ha...

Page 54: ...inating resistor at the first and the last participant of a network or a segment Please take care that those participants with the terminating resistor are supplied with power during start up and oper...

Page 55: ...e regard that you may use the Green Cable exclusively at the MP2 I jacks of the Systems 8xxx from Advantech Please regard the hints for deploying the Green Cable and the MP2 I jack in chapter 1 Start...

Page 56: ...write command stores the application program of the battery buffered RAM at the MMC The write command is controlled by means of the Siemens hardware configurator via PLC Copy RAM to ROM During the wri...

Page 57: ...disabled RUN LED off STOP LED on During the transition from STOP to RUN a call is issued to the start up organization block OB100 The length of this OB is not limited The processing time for this OB...

Page 58: ...e CPU Condition The operating mode of the CPU is STOP Place the function selector on the CPU in position ST the S LED is on Overall reset Place the function selector in the position MR and hold it in...

Page 59: ...t You may request the OVERALL_RESET by means of the menu command PLC Clear Reset In the dialog window you may place your CPU in STOP mode if this has not been done as yet and start the overall reset T...

Page 60: ...stalled into plug in location 1 or 2 see figure below 1 2 4 3 PW SF FC MC CPU 8216 DP DC 24V 1 2 RN ST MR X1 MMC R S X 2 3 4 ADAM 8216 2BP01 ER RD DE D P M P I 2 PW SF FC MC CPU 8216 DC 24V 1 2 RN ST...

Page 61: ...Open your project Click on the system you want to examine Now open the dialog window about the module state via PLC Module information Besides the possibility to recall numerous module states and perf...

Page 62: ...to enter corrections to the program Note When using the test function Monitoring the PLC has to be in RUN mode The processing of states may be interrupted by means of jump commands or by timer and pr...

Page 63: ...ossible to check the wiring and proper operation of output modules You may set outputs to any desired status with or without a control program The process image is not modified but outputs are no long...

Page 64: ...mple The chapter contains a description of the principles of the twisted pair network configuration by means of WinNCS along with an example a test program for TCP IP connections Topic Page Chapter 4...

Page 65: ...y be established by means of this cable has a star topology Every station is connected to the star coupler hub switch by means of a separate cable The hub switch provides the interface to the Ethernet...

Page 66: ...as standard CP interface Data is exchanged by means of standard handler blocks SEND and RECEIVE H1 and TCP IP communication is controlled by means of connections that are defined with the ADAM configu...

Page 67: ...buffer and transfers the data into the data buffer by means of the background communication function SEND_ALL Then the CP creates an H1 frame and transfers this to the partner station as soon as this...

Page 68: ...ard handler blocks These application programs exchange data by means of the TCP or UDP protocols of the transportation layer These themselves communicate with the IP protocol of the Internet layer IP...

Page 69: ...mmunication partner in passive mode SEND Transfers a data buffer to TCP for transmission to a communication partner RECEIVE Receives data from a communication partner CLOSE Terminates a virtual connec...

Page 70: ...equires a hub to connect the different stations A twisted pair cable has four cores twisted together in pairs The different cores have a diameter of 0 4 to 0 6 mm Twisted Pair Stecker plug Twisted Pai...

Page 71: ...related conditions encountered on site How many network stations PLCs IPCs PCs transceivers bridges if required shall be connected to the cable What is the distance between the different stations on...

Page 72: ...d on fiber optic technology FDDI Fiber Distributed Data Interface CCITT Committee Consultative Internationale de Telephone et Telegraph Amongst others this advisory committee has produced the provisio...

Page 73: ...by the IEEE Committee The last 3Byte may be defined as required The network administrator determines the Ethernet address The broadcast address to transmit messages to all stations on the network alw...

Page 74: ...ule is first turned on to calculate a unique IP address according to the following formula 00 20 D5 80 2D 7D Ethernetadresse hex 213 128 45 125 IP Adresse ADAM spez dez Note A relationship between the...

Page 75: ...ram PLC connect The CP section of the CPU 821xNET may only be configured with WinNCS from Advantech and consists of the following 3 parts The initial CP configuration configuration of connection modul...

Page 76: ...l you may configure H1 or TCP IP con nections by selecting the symbol of the station and inserting configuring the respective connection H1 Connection TCP IP Connection When all the required connectio...

Page 77: ...le for the first time this default address is changed into an individual IP address following this rules 00 20 D5 80 2D 7D Ethernetadresse hex 213 128 45 125 IP Adresse ADAM spez dez Choose IP protoco...

Page 78: ...spective handler blocks Handler block Description SEND SFC230 Transmit a job from the CPU to the CP SEND_ALL SFC236 Initiate a file transfer between the CPU and the CP RECEIVE SFC231 Reception of an o...

Page 79: ...is block is initially set to 20s Processing will be stopped if the synchronization is not completed properly within this period The following table shows the available block sizes Block size CP block...

Page 80: ...ndler blocks is required CP handler blocks are standard function blocks These provide the options required to use the communication functions in the applications of the programmable logic controllers...

Page 81: ...only incremented if the preceding send command was processed correctly completed without error The remaining data words DW1 to DW15 may be used for the transfer of user data The receiving station sto...

Page 82: ...eters that have to be defined and is divided into the following 3 parts Basic CP configuration Configuration of connection blocks Transfer of configuration data into the CP Insert two stations and sel...

Page 83: ...ADAM 8000 Manual CPU 821x Rev 1 1 You configure your H1 connection by inserting an H1 transport connection below the stations by means of and entering the following parameters for the stations Station...

Page 84: ...Manual CPU 821x Rev 1 1 4 21 You configure your TCP IP connection by inserting a TCP connection below the stations by means of and entering the following parameters for the stations TCP IP connections...

Page 85: ...nfiguration online via the network into the respective CPUs Create the system structure as shown above and start both CPUs For the data transfer please activate the online functions and click on the b...

Page 86: ...ect into the CPU RAM you should save the project additionally in the Flash ROM Otherwise the data will get lost at power off Therefore you are searching the according station in the network window Cli...

Page 87: ...program is used in both CPUs Synchronization of the interfaces In the start up OB OB100 of the CPU the interface used on the CP has to be synchronized by means of the handler block SYNCHRON OB100 ver...

Page 88: ...eiving of the data The initiation of transmission in station 1 is issued by a SEND handler block called in FC1 The partner station answers with RECEIVE FC2 By means of SEND_ALL the data will be send a...

Page 89: ...1 and DB12 are identical in design The data transfer is realized via MPI If your programming device has no MP interface you may also use the Green Cable ADAM 8950 0KB00 from Advantech The Green Cable...

Page 90: ...modules is established This is indicated by the COMM LEDs Start the Siemens STEP 7 manager and execute the following steps to monitor the transmitting job PLC Monitor Modify Value In the Operand colum...

Page 91: ...n this condition data communication with the PLC is inhibited and it is only enabled after synchronization has taken place The boot time of the CPU 821xNET including the CP amounts to app 18s With eve...

Page 92: ...e the user has to define the exact length of the data that will be received Jobs with a priority of 1 may send and or receive a maximum quantity of data as defined by the SYNCHRON HTB Jobs of this pr...

Page 93: ...this The PLC application requires a defined size for the reception of data and the wildcard length is not permitted The size of the receive block of Prio1 RECEIVE jobs is defined implicitly by the pr...

Page 94: ...a DB MB EB AB ORG identifier 01h 02h 03h 04h Description Source destination data from into data block in main memory source destination data from into flag area Source destination data from into proce...

Page 95: ...used Request message System identifier S 5 Header length 16d Ident OP code 01 OP code length 03 OP Code 03 ORG block 03 ORG block length 08 ORG identifier DBNR Start address H L Length H L Dummy block...

Page 96: ...cation data With wildcard lengths the actual length of the data is retrieved from the respective TRADA header With the TRADA functionality the following header will precede a SEND job and it is analyz...

Page 97: ...se please start TCPTEST EXE The test program is executed and displays the following window The menu has the appearance of tab sheets The respective dialog window may be displayed by left clicking with...

Page 98: ...ctive connection Save Conn5 Save Win Pos saves the current window position Show Hints When you place the cursor on an input field or on a button a hint is displayed if you selected Show Hints This win...

Page 99: ...s for remote and local Time 10mSec Definable interval for cyclic read operations OrgKennung Type of the source block DBNr Number of the source block AnfAdr Start address of the source block Len Word l...

Page 100: ...r cyclic write operations The minimum timer value for cyclic writes is 5 OrgKennung Type of destination block DBNr Number of destination block AnfAdr Start address of destination block Len Word length...

Page 101: ...ly display UDP messages AutoListen If you select AutoListen the program switches to receive mode Every message received from the remote CP is displayed in the list Interruptions of the connection are...

Page 102: ...erations The mini mum timer value for cyclic writes is 5 Tick box UDP This tick mark selects unsecured communications No virtual connections are used by unsecured communication links In this manner yo...

Page 103: ...his may be seen Hardware Stop RUN STOP lever at the CP is in STOP position The CP is not remoteable with the test program Hardware Run RUN STOP lever at the CP is in RUN position The CP is remoteable...

Page 104: ...is chapter ends with information to the operating modes of the DP master and to the commissioning The following text describes Principles of Profibus DP Proyect engineering of a CPU 821xDPM Deployment...

Page 105: ...s from the various slaves and writes new output information into the slaves Profibus distinguishes between active stations masters and passive stations slaves Master equipment Master equipment control...

Page 106: ...The master slave data transfer is divided into parameterization configura tion and data transfer phases Before a DP slave is included into the data transfer phase the master verifies during the param...

Page 107: ...cal waveguide system uses monochromatical light impulses The optical waveguide is totally independent from disturbing voltage from other machines An optical waveguide system is built up linear Every m...

Page 108: ...of our modules at your disposal by including the GSD file into the STEP 7 manager To be compatible with the STEP 7 projecting tool from Siemens you have to execute the following steps for the System 8...

Page 109: ...e deployment of the Profibus DP slaves of the Systems ADAM 8xxx from Advantech you have to include the modules into the hardware catalog by means of the GSD file from Advantech The following section d...

Page 110: ...Profibus address 1 to this slave Place the CPU 821x 2BM01 from Advantech at the plug in location 0 in your configurator The plug in location 0 is mandatory Now the project engineering of your Profibus...

Page 111: ...icture shows the parameterization of the positioning module FM 8254 For the project engineering of Profibus DP slaves coupled at the DP master of the CPU 821xDPM you approach analog to the ADAMCPU821x...

Page 112: ...e activated terminating resistors are always supplied with voltage during start up and operation Connect your PU resp your PC via MPI with the CPU If your programming device has no MPI interface you m...

Page 113: ...the PC and the MP2 I interface of the CPU Attention Please regard that you may use the Green Cable exclusively at the MP2 I interfaces of the Systems ADAM 8xxx from Advantech Please regard the notes...

Page 114: ...If there is a plugged MMC in the CPU the content of the battery buffered RAM is transferred to the MMC by means of a WRITE command The write command is started from the hardware configurator from Siem...

Page 115: ...are blinking At invalid parameters the DP master switches to RUN and monitors a parameterization error via the IF LED Now the DP master is linked up at the bus with the following default bus paramete...

Page 116: ...up behavior is following The following picture shows the approach once more 3 Sec R S PW SF FC MC RN ST MR 3Sec RN ST MR RN ST MR RN ST MR R S PW SF FC MC R S PW SF FC MC R S PW SF FC MC When the CPU...

Page 117: ...a buffer of max 30 days Is this time exceeded there may be a total discharge of the battery and the battery buffered RAM is erased Now the CPU proceeds an overall_reset If a MMC is plugged in the appl...

Page 118: ...d the CPU 821xDPM concludes the chapter This chapter contains a description of the principles of Profibus DP configuration and parameterization of a CPU 821xDP diagnostic and status messages assembly...

Page 119: ...the input values from the various slaves and writes new output information into the slaves Profibus distinguishes between active stations masters and passive stations slaves Master equipment Master eq...

Page 120: ...en the master and the slaves assigned to the respective master When you configure the system you define which slaves are assigned to a certain master You may also specify which DP slave is included in...

Page 121: ...output data from the PA are transferred to the output modules After the data exchange is completed the PE is transferred to the sending buffer buffer send and the content of the input buffer buffer re...

Page 122: ...re acquired together and they are transmitted together Byte wise consistency is sufficient for the processing of digital signals Where the length of the data exceeds a single byte e g analog values th...

Page 123: ...network The optical waveguide system uses monochromatically light impulses The optical waveguide is totally independent from disturbing voltage from other machines An optical waveguide system is buil...

Page 124: ...igurator from Siemens is required The address allocation and the parameterization of the directly plugged in System 82xx modules takes place via the STEP 7 manager from Siemens in form of a virtual Pr...

Page 125: ...art of the STEP 7 projecting tool from Siemens for project engineering The modules parameterizable via this tool are in the hardware catalog of this tool For the deployment of the Profibus DP slaves o...

Page 126: ...ens you have to include the CPU 821xDP explicitly like mentioned above Add the System ADAM_CPU821x to your subnet The module is to find under PROFIBUS DP Additional Field devices I O DP8000 Assign the...

Page 127: ...slave Details are to find in the chapter DP slave parameters Attention Please regard that the lengths of the data areas are identical at the master and the slave project engineering Due to the restri...

Page 128: ...ADAM_CPU821xDP Assign a valid Profibus address Assign memory space from the address area of the CPU to the Profibus section in form of modules for in and output Save your project and transfer it into...

Page 129: ...th values for in and output area have to be identical to the byte values of the master configuration Otherwise there is no Profibus communication possible and the master notes a slave failure Slave Sy...

Page 130: ...ies no CPU memory space for the input area The parameter data are an extract of the parameter telegram The parameter telegram is created during the master configuration and is send to the slave when t...

Page 131: ...diagnostics by controlled access to this area Note More detailed information about the structure and the control possibilities on diagnostic messages are to find under Diagnostic functions The recent...

Page 132: ...e CPU you may start the diagnostics and modify the diagnostic data Diagnostic data consists of standard diagnostic data Byte 0 5 equipment related diagnostic data Byte 6 15 The structure of the diagno...

Page 133: ...transfer Bit 2 configuration data is not identical Bit 3 slave got extern diagnostic data Bit 4 slave does not provide this function Bit 5 fixed at 0 Bit 6 wrong parameterization Bit 7 fixed at 0 1 Bi...

Page 134: ...te in the process picture of the CPU This data may be overwritten and forwarded to the master In case of a diagnostic action the contents of Byte 11 15 of the equipment related diagnostic data will be...

Page 135: ...ata found Response control active 0 Response control not active 1 Response control activated by DP master Status Profibus data transfer 0 Data transfer error 1 Data transfer via Profibus active reserv...

Page 136: ...tion data and the number of parameter bytes is analyzed The configuration is only accepted as being correct if these are equal and if no more than 31Byte of parameter data is transferred Status indica...

Page 137: ...inated at both ends Masters and slaves may be installed in any sequence Note When using optical participants you should place a cover over the socket for the next station at the end of the bus to avoi...

Page 138: ...2 stations Different segments are connected by means of repeaters That maximum length of a segment depends on the data communication rate The rate of data transfer of a Profibus DP link is set to a va...

Page 139: ...standard Profibus cable type B according to EN50170 Under the order no ADAM 8905 6AA00 Advantech offers the EasyStrip deisolating tool that makes the connection of the EasyConn much easier Attention T...

Page 140: ...nly viable if the slower line at the left is connected to slaves that do not require up to date data This portion of the line should also not be connected to modules that issue alarms 3 Input output p...

Page 141: ...system More than one master and multiple slaves connected to one bus 3 Input output periphery CPU 21x DP 5 Input output periphery CPU 21x DP CPU IM 208 5 CPU IM 208 1 3 IM 253 1 Input output peripher...

Page 142: ...purpose To configure the System 82xx Profibus slave modules from Advantech you need to include the according GSD file into the configuration tool from Siemens The System 82xx peripheral modules that a...

Page 143: ...he MC LED on the CPU blinks Due to the system the successful writing is signalized too soon The write command has only been completed when the LED extinguishes Attention Please regard the hints for de...

Page 144: ...e backplane bus On the other hand the CPU 8214DP should count from 00h to FFh This count shall also be saved in the output area of the CPU slave and be transferred to the master via Profibus This valu...

Page 145: ...location 1 For linking up the CPU 8214DP you have to execute the following steps after including the GSD file Add the Profibus slave CPU82xxDP address 3 The DP slave is in the hardware catalog under...

Page 146: ...82xx Start the hardware configurator from Siemens Configure a CPU 315 2DP with DP master system address 2 Add a Profibus slave DP8000 at address 1 Include the CPU 8214 2BP01 at the plug in location 0...

Page 147: ...ansferred I correctly from the slave CPU BEB No End Data exchange via Profibus L EB 11 Load input byte 11 output data of the CPU214DP and T AB 0 transfer to output byte 0 BE Read counter value from MB...

Page 148: ...id receive data BEB No End L B 16 FF Load control value and compare L PEB 30 to control byte I 1st input byte BEB Received data does not contain valid values L B 16 FE Control byte for master CPU T PA...

Page 149: ...Please regard that some ADAM specific SFCs are only integrated in certain CPUs For example the SFCs for high speed counter and pulse duration modulation are only integrated in the CPUs of the System 8...

Page 150: ...FC 224 HSC 7 14 SFC 225 HF_PWM 7 16 SFC 227 TD_PRM 7 18 SFC 228 RW_KACHEL 7 20 Page frame communication Parameter 7 22 Page frame communication Parameter transfer 7 25 Page frame communication Source...

Page 151: ...pth for blocks The following organization blocks OBs are available OB Description OB 1 Free cycle OB 10 Clock alarm OB 20 Delay alarm OB 35 Prompter alarm OB 40 Process alarm OB 80 Cycle time exceeded...

Page 152: ...FILL Predefine field inside work memory SFC 22 CREAT_DB Create data block SFC 23 DEL_DB Delete data block SFC 24 TEST_DB Test data block SFC 28 SET_TINT Set clock alarm SFC 29 CAN_TINT Cancel clock al...

Page 153: ...s only for analog digital blocks FM350 CP340 not possible via Profibus SFC 57 PARM_MOD Parameterize block only for analog digital blocks FM350 CP340 not possible via Profibus SFC 58 WR_REC Write recor...

Page 154: ...223 PWM Parameterize pulse duration modulation SFC 224 HSC Parameterize high speed counter SFC 225 HF_PWM Parameterize HF pulse duration modulation up to 50kHz SFC 227 TD_PRM Parameterization for TD2...

Page 155: ...irectory and select Extract The following structure is created in the destination directory To de archivate the SFC library you start the STEP 7 manager from Siemens Via File De archivate you open a d...

Page 156: ...blocks This may be avoided by formatting the MMC before the write access At a write access from the CPU to the MMC the data is always stored unfragmentated When opening an already existing file you h...

Page 157: ...rted at this time Return Value Word that returns a diagnostic error message 0 means OK See the table below for the concerning messages Value Description Diagnostic messages 0000h no errors 0001h File...

Page 158: ...address inside the file on the MMC from where on the data has to be transferred to the CPU During data transfer this Bit remains set The Bit is reset as soon as the data transfer is complete Return Va...

Page 159: ...beginning of the data inside the file on the MMC where the data is written to During data transfer this Bit remains set The Bit is reset as soon as the data transfer is complete Return Value Word whe...

Page 160: ...issues this via the according output channel The SFC returns a certain error code You can see the concerning error messages in the table at the following page The PWM parameters have the following re...

Page 161: ...riod 1 Promille 1 Timebase If the calculated pulse duration is no multiplication of the timebase it is rounded down to the next smaller time base limit Value range 0 1000 Via MinLen you define the min...

Page 162: ...lse Value range true false Fix the counting direction Hereby is 0 Counter is deactivated means Enable false 1 count up 2 count down Here you may preset a counter content that is transferred to the acc...

Page 163: ...not configured as counter Error in the hardware configuration 8008h Parameter Direction outside the permissible range 8009h Parameter Channel outside the permissible range 9001h Internal error There w...

Page 164: ...length The CPU determines an pulse series with an according pulse break relation and issues this via the according output channel The SFC returns a certain error code You can see the concerning error...

Page 165: ...e next smaller time base limit Value range 0 1000 Via MinLen you define the minimal pulse length Switches are only made if the pulse exceeds the here fixed minimum length Value range 0 60000 Via the p...

Page 166: ...able from Advantech The call of the SFC 227 specifies the terminal to communicate with To call the SFC you have to transfer the following parameters MPI address Enter the MPI address of the connected...

Page 167: ...UT 16 Byte TD200 Output Periphery 128 Byte OFFSET_OUTPUT 16 Byte TD200 Return Value Type the bit memory byte marker byte where the resulting message should be stored For specification of the error mes...

Page 168: ...ng up proprietary communication systems and is completely at the user s disposal Please regard that a write access to the page frame area influences a communication directly Page frame i e Kachel no T...

Page 169: ...to 4Byte starting with Byte 712 in page frame 2 The read 4Byte are stored in DB10 starting with Byte 2 Herefor the following call is required CALL SFC 228 K_NR 2 OFFSET 712 R_W 0 SIZE 4 RET_VAL MB10 V...

Page 170: ...ew user application memory space short runtimes of the blocks The handling blocks don t need bit memory area time areas counter areas All handling blocks described in the following use an identical in...

Page 171: ...ctly specified DB Kind of parameterization direct indirect This parameter defines the kind of data on which the pointer QUANF points 0 QANF points directly to the initial data of the source res destin...

Page 172: ...TE 10 Block size During the boot process the stations agree about the block size size of the data blocks by means of SYNCHRON A high block size high data throughput but longer run times and higher cyc...

Page 173: ...pointing to other parameter fields data blocks or data words The parameters SSNR ANR IND and BLGR are of the type integer so you may parameterize them indirectly Direct parameter transfer CALL SFC 230...

Page 174: ...10 P A b 0 BYTE c P A 0 0 BYTE 2 P E b 0 BYTE c P E 20 0 BYTE 1 DB MB AB EB Definition P DBa a means the DB No from where the source data is fetched or where to the destination data is transferred P M...

Page 175: ...source and destination parameters and ANZW are stored in a DB in a sequential order QANF ZANF valid DB No 0 32767 0 32767 Data word Definition DW No where the stored data starts DW No where the store...

Page 176: ...ECEIVE blocked 1 RECEIVE released Bit 1 order commissioning is running 0 SEND FETCH released 1 SEND FETCH blocked Bit 2 Order ready without errors Bit 3 Order ready with errors Data management handlin...

Page 177: ...been commissioned e g receipt received Analyze Per handling blocks A new order is only send when the order before is completely commissioned Per user when you want to know if triggering a new order is...

Page 178: ...are transferred in blocks during more AG cycles To ensure data consistency you should proof that the data block isn t in transfer any more before you change the content Data transmission is active Se...

Page 179: ...No 3 AG area too small Q ZANF and Q ZLAE overwrite the range boundaries Handling with data blocks the range boundary is defined by the block size With flags timers counters etc the range size depends...

Page 180: ...rmal system message This order is a READ WRITE PASSIV and can not be started from the AG F Order not found The called order is not parameterized on the CP This error may occur when the SSNR A No combi...

Page 181: ...at the connection of the communication order is not yet established Together with the state index A SEND RECEIVE and FETCH are blocked Indicator word X 0 X 8 The connection has been established again...

Page 182: ...A X D X 8 Messages at RECEIVE State under H1 Prio 0 1 Prio 2 Prio 3 4 State under TCP IP Prio 1 Prio 2 Prio 3 after reboot 0 A 0 A 0 A 0 A 0 0 0 1 after connection start X 0 X 4 X 0 0 9 after initial...

Page 183: ...ANF PAFE has the following structure Byte Bit 7 Bit 0 0 Bit 0 error 0 no error 1 error error No in Bit 4 to Bit 7 Bit 1 Bit 3 reserved Bit 4 Bit 7 error No 0 no error 1 wrong ORG Format 2 area not fou...

Page 184: ...ased the order Bit order active in ANZW 0 During block stand by only the indicator word is updated If the CP is able to take over the data directly the SEND block transfers the requested data in one s...

Page 185: ...by only the indicator word is updated The RECEIVE block reacts different depending from the kind of supply and the CP reaction If the CP transmits a set of parameters although the RECEIVE block itsel...

Page 186: ...nter parameter The partner station provides the Source data and transmits them via SEND_ALL back to the requesting station Via RECEIVE_ALL the data is received and is stored in Destination The update...

Page 187: ...the CP it just transfers the announcements in the order status to the parameterized indicator word The block is independent from the VKE and should be called from the cyclic part of the application If...

Page 188: ...s logical interface e g deletes all order data and interrupts all active orders With a direct function ANR 0 only the specified order will be reset on the logical interface The block depends on the VK...

Page 189: ...un times it is convenient to split large data amounts into smaller blocks for transmitting them between CP and CPU You declare the size of this blocks by means of block size A large block size high da...

Page 190: ...ator word of the block the indicator word that is parameterized in the SEND_ALL block the current order number is stored 0 means stand by The amount of the transmitted data for one order is shown in t...

Page 191: ...The receiving amount is shown in the following word In the indicator word of the block the indicator word that is parameterized in the RECEIVE_ALL block the current order number is stored In the stand...

Page 192: ...just transfers the announcements in the order status to the parameterized indicator word The block is independent from the VKE and should be called from the cyclic part of the application If ANR 0 th...

Page 193: ...and abbreviation list Structure of the registers and addressing examples Instruction list ADAM specific diagnostic entries Event IDs Topic Page Chapter 8 Instruction list 8 1 Alphabetical instruction...

Page 194: ...1 I 8 11 R 8 11 D 8 11 I 8 11 R 8 11 D 8 11 I 8 11 R 8 11 D 8 11 I 8 11 R 8 11 8 19 D 8 26 I 8 26 R 8 26 D 8 26 I 8 26 R 8 26 D 8 26 I 8 26 R 8 26 D 8 26 I 8 26 R 8 26 D 8 26 I 8 26 R 8 26 I 8 26 D 8...

Page 195: ...14 INC 8 24 INVD 8 25 INVI 8 25 ITB 8 25 ITD 8 25 JBI 8 21 JC 8 21 JCB 8 21 JCN 8 21 JL 8 22 JM 8 21 JMZ 8 21 JN 8 21 JNB 8 21 JNBI 8 21 JO 8 21 JOS 8 21 JP 8 21 JPZ 8 21 JU 8 21 JUO 8 21 JZ 8 21 L 8...

Page 196: ...8 25 RND 8 25 RND 8 25 RRD 8 18 RRDA 8 18 S 8 19 8 35 SA 8 33 SAVE 8 20 SD 8 33 SE 8 33 SET 8 20 SIN 8 12 SLD 8 18 SLW 8 18 SP 8 33 SQR 8 12 SQRT 8 12 SRD 8 18 SRW 8 18 SS 8 33 SSD 8 18 SSI 8 18 T 8...

Page 197: ...tion code CC1 Condition code D area crossing register indirect addressed double word D IEC date constant DB Data block DBB Data byte in the data block DBD Data double word in the data block DBW Data w...

Page 198: ...eriphery input byte direct periphery access PID Periphery input double word direct periphery access PIW Periphery input word direct periphery access PQB Periphery output byte direct periphery access P...

Page 199: ...Bit 0 to Bit 7 ACCUx LH Bit 8 to Bit 15 ACCUx HL Bit 16 to Bit 23 ACCUx HH Bit 24 to Bit 31 The address registers contain the area internal or area crossing addresses for the register indirect addres...

Page 200: ...e addressing L 27 Load 16Bit integer constant 27 in ACCU1 L L 1 Load 32Bit integer constant 1 in ACCU1 L 2 1010101010101010 Load binary constant in ACCU1 L DW 16 A0F0_BCFD Load hexadecimal constant in...

Page 201: ...on input address is calculated pointer value in address register 1 pointer P 12 2 Register indirect area crossing addressing For the area crossing register indirect addressing the address needs an add...

Page 202: ...esses 7 LAR1 P 8 2 A I AR1 P 10 2 Result The input 18 4 is addressed by adding the byte and bit addresses Example when sum of bit addresses 7 L MD 0 at will calculated pointer e g P 10 5 LAR1 A I AR1...

Page 203: ...umbers The result is in ACCU1 D BR CC1 CC0 OV OS OR STA RLO FC Add up two integers 32Bit 1 ACCU1 ACCU2 ACCU1 D Y Y Y Y Subtract two integers 32Bit 1 ACCU1 ACCU2 ACCU1 D Multiply two integers 32Bit 1 A...

Page 204: ...l function is in ACCU1 The instructions may be interrupted by alarms SIN 1 BR CC1 CC0 OV OS OR STA RLO FC Calculate the sine of the real number 1 ASIN 2 Y Y Y Y Calculate the arcsine of the real numbe...

Page 205: ...cks without parameter 1 FC r transfer Parameter FB FC call via parameters CC FB r BR CC1 CC0 OV OS OR STA RLO FC Conditional call of blocks without parameter 1 FC r Y transfer Parameter 0 0 1 0 FB FC...

Page 206: ...e of the RLO is compared with the signal state of the instruction or edge bit memory FP detects a change in the RLO from 0 to 1 FN detects a change in the RLO from 1 to 0 FP I Q a b 0 0 to 127 7 BR CC...

Page 207: ...2 LB a 0 to 1043 local data byte 2 DBB a 0 to 8191 data byte 2 DIB a 0 to 8191 instance data byte 2 in ACCU1 2 g AR1 m register indirect area internal AR1 2 g AR2 m register indirect area internal AR...

Page 208: ...parameters 2 L Load k8 8Bit constant in ACCU1 LL 1 k16 16Bit constant in ACCU1 L 2 k32 32Bit constant in ACCU1 3 Parameter Load constant in ACCU1 addressed via parameters 2 L 2 n Load 16Bit binary con...

Page 209: ...recent content of ACCU1 is saved in ACCU2 The status word is not affected L T f 0 to 127 Load time value 1 2 Timer parameter Load time value addressed via parameters 2 L C f 0 to 255 Load counter val...

Page 210: ...ome free are provided with zeros SRW Shift the contents of ACCU1 L to the right 1 SRW 0 15 Positions that become free are provided with zeros SRD Shift the contents of ACCU1 to the right 1 SRD 0 32 Po...

Page 211: ...2 AR2 m area crossing AR2 2 Parameter via parameters 2 R BR CC1 CC0 OV OS OR STA RLO FC Reset I Q a b 0 0 to 127 7 Y input output to 0 1 2 M a b 0 0 to 1023 7 0 Y 0 set bit memory to 0 1 2 L a b 0 0 t...

Page 212: ...ADAM 8000 Manual CPU 821x Rev 1 1 Instructions directly affecting the RLO Status word The following instructions have a directly effect on the RLO CLR BR CC1 CC0 OV OS OR STA RLO FC Set RLO to 0 1 0...

Page 213: ...if RLO 0 2 0 1 1 0 JCB LABEL BR CC1 CC0 OV OS OR STA RLO FC Jump if RLO 1 2 Y Save the RLO in the BR Bit JNB LABEL Y 0 1 1 0 Jump if RLO 0 2 Save the RLO in the BR Bit JBI LABEL BR CC1 CC0 OV OS OR S...

Page 214: ...T Transfer the contents of ACCU1 LL to IB a 0 to 127 input byte 1 2 QB a 0 to 127 output byte 1 2 PQB a 0 to 1023 periphery output byte 1 2 MB a 0 to 1023 bit memory byte 1 2 LB a 0 to 1043 local data...

Page 215: ...Parameter via parameters 2 Load and transfer instructions for address register Load a double word from a memory area or a register into AR1 or AR2 LAR1 Load the contents from ACCU1 1 AR2 address regi...

Page 216: ...CC1 CC0 OV OS OR STA RLO FC Transfer ACCU1 Bits 0 to 8 into status word Y Y Y Y Y Y Load instructions for DB number and DB length Load the number length of a data block to ACCU1 The old contents of AC...

Page 217: ...CCU1 from integer 16Bit to integer 1 32Bit Int To Doubleint ITB BR CC1 CC0 OV OS OR STA RLO FC Convert contents of ACCU1 from integer 16Bit to BCD 1 0 to 999 Int To BCD DTB Y Y Convert contents of ACC...

Page 218: ...CU2 L ACCU1 L 1 I ACCU2 L ACCU1 L 1 I ACCU2 L ACCU1 L 1 Comparison instructions with integer 32Bit Status word Comparing the integer 32Bit in ACCU1 and ACCU2 RLO 1 if condition is satisfied D BR CC1 C...

Page 219: ...indirect area internal AR2 2 AR1 m area crossing AR1 2 AR2 m area crossing AR2 2 Parameter via parameters 2 AN BR CC1 CC0 OV OS OR STA RLO FC AND operation of signal state 0 I Q a b 0 0 127 7 Y Y Y I...

Page 220: ...CC1 CC0 OV OS OR STA RLO FC EXCLUSIVE OR operation at signal state 1 I Q a b 0 0 127 7 Y Y Input output 2 M a b 0 0 1023 7 0 Y Y 1 Bit memory 2 L a b 0 0 1043 7 Local data bit 2 DBX a b 0 0 8191 7 da...

Page 221: ...A BR CC1 CC0 OV OS OR STA RLO FC AND left parenthesis 1 AN Y Y Y Y AND NOT left parenthesis 1 O 0 1 0 OR left parenthesis 1 ON OR NOT left parenthesis 1 X EXCLUSIVE OR left parenthesis 1 XN EXCLUSIVE...

Page 222: ...r 1 2 Timer para Timer addressed via parameters 2 Counter p Counter addressed via parameters O BR CC1 CC0 OV OS OR STA RLO FC OR operation at signal state T f 0 to 127 Y Y Timer 1 2 C f 0 to 255 0 Y Y...

Page 223: ...and CC0 0 or CC1 1 and CC0 0 1 UO unordered math instruction CC1 1 and CC0 1 1 OS OS 1 1 BR BR 1 1 OV OV 1 1 AN BR CC1 CC0 OV OS OR STA RLO FC AND operation at signal state 0 0 Y Y Y Y Y Y Y Y Result...

Page 224: ...1 X BR CC1 CC0 OV OS OR STA RLO FC EXCLUSIVE OR operation at signal state 1 0 Y Y Y Y Y Y Y Result 0 CC1 0 and CC0 0 1 0 0 Y Y 1 Result 0 CC1 1 and CC0 0 1 0 Result 0 CC1 0 and CC0 1 1 0 Result 0 CC1...

Page 225: ...onstant 2 AD AND ACCU2 1 AD k32 AND 32Bit constant 3 OD OR ACCU2 1 OD k32 OR 32Bit constant 3 XOD EXCLUSIVE OR ACCU2 1 XOD k32 EXCLUSIVE OR 32Bit constant 3 Timer instructions Time instructions Status...

Page 226: ...ction list CPU ADAM 821x Command Operand Parameter Status word Function Length in BR CC1 CC0 OV OS OR STA RLO FC words Instruction depends on Instruction influences 8 34 ADAM 8000 Manual CPU 821x Rev...

Page 227: ...L res in the address transferred as parameter S C f 0 to 255 BR CC1 CC0 OV OS OR STA RLO FC Presetting of counter on edge change from 0 to 1 1 2 Counter p Y 2 R C f 0 to 255 0 0 Reset counter to 0 1...

Page 228: ...rt some additional specific entries in form of event IDs To monitor the diagnostic entries you choose the option PLC Module Information in the STEP 7 Manager Via the register Diagnostic Buffer you rea...

Page 229: ...arsing 0xE006 Error at DP slave information parsing 0xE007 Configured in output bytes do not fit in the peripheral area DP Slave High speed counter 0xE008 Error at High speed counter information parsi...

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