CIO-32
6
The hardware architecture of the CIO-32 is divided in 3 main sections:
• The IP bus interface, controlling the timing access of the CIO controllers
and the on-board memory.
• The CIO controllers, Zilog Z8536.
• The 2 kByte of non-volatile memory including the identification ROM and
module specific data.
ID ROM
2 kB
EEPROM
IP Bus
Interface
CIO (0)
controller
Z8536
IP Bus
CIO (1)
controller
Z8536
I/O interface
Port A, B (8-bit)
Port E (4-bit)
Timer 1, 2, 3 (16-bit)
Port C, D (8-bit)
Port F (4-bit)
Timer 4, 5, 6 (16-bit)
3.2. IP spaces
The following table shows the four CIO-32 memory spaces.
MEM space
(2 kByte - 64 Byte) of non-volatile memory
ID space
IP identification codes
I/O space
CIO controllers access
INT Ack
Interrupt acknowledge
The base address of these spaces is depending on the IP carrier.
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