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Actel Silicon Explorer II User Manual Download Page 40

Appendix D: Troubleshooting

34

Q: How is the checksum of the device read?

A: The checksum of most devices is read through the SDO pin. For 

information about the location of SDO pins in all Actel Devices 
please refer to “Location of the SDO Pin” on page 21. 

ACT1 and the 40MX pins do not have an SDO pin. In order to read 
the checksum from ACT1/40MX devices the PRA on the device 
must be connected to the SDO pin of the Silicon Explorer.

Q: What are the power requirements for Silicon Explorer II?

A: Silicon Explorer II must be connected to a power supply of 5V for 

5V tolerant devices, 3.3V for 3.3V tolerant devices, and 2.5V for 
2.5V tolerant devices. 

Summary of Contents for Silicon Explorer II

Page 1: ...Actel Silicon Explorer II User s Guide Windows Environments...

Page 2: ...EL Customer Service 408 739 1010 Customer Service FAX 408 522 8044 Customer Applications Center 800 262 1060 Customer Applications FAX 408 739 1540 Actel Europe Ltd Maxfli Court Riverside Way Camberle...

Page 3: ...Actel Silicon Explorer II User s Guide Windows Environments...

Page 4: ...lar purpose Information in this document is subject to change without notice Actel assumes no responsibility for any errors that may ap pear in this document This document contains confidential propri...

Page 5: ...ware 9 Using the Command Module 10 Using the Analyze Module 13 A Debugging SX SX A eX Devices Using Silicon Explorer II 17 Probe Circuit Control Pins 17 Diagnostic Pin Consideration 18 B Location of t...

Page 6: ......

Page 7: ...all the observable nets in the FPGA Select the desired net in the list and click the PRA or PRB button to display the signal on the Analyze module The Command module also reads back the design s chec...

Page 8: ...se the desired port COM1 through COM4 from the Port drop down list in the Device menu The software continuously polls the hardware for activity Setting the port to the Demo mode prevents the applicati...

Page 9: ...SE II See Table 1 1 for a list of possible power configurations When you apply power the yellow heart beat LED on Silicon Explorer II begins to blink Actel designed Silicon Explorer II hardware to wi...

Page 10: ...Connector Types Silicon Explorer II has a 22 pin 18 channels a clock VIO GND and clock GND and a 16 pin connector for controlling the ActionProbe circuitry and reading the design checksum Silicon Exp...

Page 11: ...IN lead to the target clock which requires a continuous signal If the clock is greater than 20 MHz connect the CLK GND twisted pair to a ground point near the CLK lead Probe Leads Connect the probe le...

Page 12: ...to connect Silicon Explorer II to the ACT1 A40MX devices Figure 1 3 Table 1 4 Matching Probe Pins to Device Pins a a ERRORn CONn M2 M1 M0 pins are not required for use with Silicon Explorer II Probe...

Page 13: ...rer II Setup Figure 1 3 ACT2 XL ACT3 DX A42MX Silicon Explorer II Setup ACT1 A40MX Silicon Explorer Setup Silicon Explorer MODE SDI DCLK SDO PRA PRB Serial Connection to Windows PC 16 Logic Analyzer C...

Page 14: ...tel recommends that you use a series 70 ohm termination on all the probe connectors TDI TDO TCK TMS PRA PRB The 70 ohm series termination is used to prevent data transmission corruption during probing...

Page 15: ...s in the FPGA Use the Command module to verify that you programmed the correct design in the FPGA The Analyze module is an 18 channel logic analyzer that automatically displays the signals for both pr...

Page 16: ...with the probe Figure 2 2 Command Module Explore the FPGA The following procedures describe how to use the Command module to examine an Actel FPGA To open a probe file 1 Launch Silicon Explorer Selec...

Page 17: ...the Analyze window To export a probe file from Designer 1 Launch Designer 2 Open your design file 3 Open the Export dialog box Select Export from the File menu to view the Export dialog box Figure 2 3...

Page 18: ...selected node to the probe pin and switches the corresponding analyzer input to the probe connector The Analyze module displays the net name You can modify the tree information to reflect the design s...

Page 19: ...27 for more information about the limitations in probing Actel devices using Silicon Explorer Using the Analyze Module Note This section does not apply to Silicon Explorer II Lite since it does not co...

Page 20: ...rameters click the Run button red triangle to begin acquisition The analyzer begins capturing data After you acquire the initial 64K samples sampling continues until Silicon Table 2 2 Acquisition Para...

Page 21: ...are available in the scroll bars tool bar or keyboard control In addition dragging a box in the display area zooms the window Table 2 3 lists keyboard equivalents Place cursors by clicking in the disp...

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Page 23: ...en debugging SX SX A or eX devices Probe Circuit Control Pins The Silicon Explorer II tool uses the IEEE 1149 1 ports TDI TCK TMS and TDO to select the desired nets for debugging The user assigns the...

Page 24: ...gnostic Pins Configuration To Access the Device Variations Dialog Box in Designer 1 Launch Designer 2 Open your Design 3 Select Device Setup under the Options Menu The Device Selections dialog box app...

Page 25: ...unction as user I Os or JTAG pins When you select Flexible JTAG mode you disable the internal pull up resistors on the TMS and TDI pins Note that you require an external 10K Ohm pull up resistor on th...

Page 26: ...If you assign user I Os to the PRA and PRB pins and select the Reserve Probe Pin option the Layout tool will override the Reserve Probe Pin option Design Considerations Avoid using the TDI TCK TDO PRA...

Page 27: ...21 B Location of the SDO Pin Figure B 1 SDO Pin Location Table...

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Page 29: ...ero state all of the mode registers and control path flip flops are directly held in the inactive state guaranteeing that the device is in normal operating mode Note that there is no guarantee as to t...

Page 30: ...his effect has been observed Under normal operating conditions MODE low and VPP high the VPP signal is used to bias transistors in the peripheral control circuitry of the FPGA and does not directly ac...

Page 31: ...xcessive current Also we have found that the VPP pin is the most sensitive pin to ESD on the RH1020 and RH1280 Actel recommends that you connect the VPP pin be directly to the VCC Additionally verify...

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Page 33: ...ow heartbeat If it isn t flashing make sure you have properly connected an adequate power supply Q It s flashing but still N C Why A There are a number of things that prevent you from establishing com...

Page 34: ...Saving in the CMOS setup menu Q When the Explore window is open my other Windows programs run slowly Why A If the Explore window is open but not connected or powered up then the system is constantly t...

Page 35: ...ast twice the frequency of the fastest changing signal The maximum frequency at which the signal can be sampled is 100 MHz which limits the frequency of the device to 50MHz If a higher sampling freque...

Page 36: ...gnal is inverted We do not have a specific break point in the lot numbers for A10xxB devices however if you provide the lot number to us we will try to determine if that lot has inverted probe signals...

Page 37: ...es which have their security fuse programmed Q Can I use the probe pins as regular I Os A All of the probe pins can be used as user I O except for the MODE and TMS pins Once the device enters probe mo...

Page 38: ...ing at higher frequencies however causes the Silicon Explorer to consume more power Q What is the best way to find nets A The best way to find the nets in the Silicon Explorer is to use the Filter opt...

Page 39: ...con Explorer Probe Pilot A You can connect the Silicon Explorer to the device by either implementing a probe connector on the board for use with the ribbon connector or by connecting the device to the...

Page 40: ...ion of the SDO Pin on page 21 ACT1 and the 40MX pins do not have an SDO pin In order to read the checksum from ACT1 40MX devices the PRA on the device must be connected to the SDO pin of the Silicon E...

Page 41: ...e Module 13 Exporting Probe Files 11 F Flexible JTAG Mode 19 L Logic Analysis 5 P Pin Layout 33 Power Configurations 3 Power Source 3 ProASIC Support 31 Probe Connector Pin Out 5 Probe Leads Connectin...

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