XVME-6300
6U VME Intel i7 Core Processor Board
Acromag, Inc. Tel: 248-295-0310
- 26 -
www.acromag.com
(Example: VMEbus Slave Image 1 BS=A0000hBD= 400000hTO = 060000h)
This rather awkward mapping defined by the PC/AT architecture can also be over come if
the VMEbus Slave Image window is always configured with a 1Mbyte Translation Offset.
From a user and software standpoint this is always more desirable because the interrupt
vector table, system parameters and communication buffers (keyboard) are placed in low
DRAM. This provides for more system protection.
Caution: When setting up slave images the address and other parameters should be set first. Then only
after the VMEbus slave image is set up correctly should the VMEbus slave image be enabled. If a slave
image is going to be remapped disable the slave image first then reset the address. After the image is
configured correctly enable the image again.
The VMEbus slave cycle becomes a master cycle on the PCI bus. The PCI bus arbiter is the PEX8114. It
arbitrates between the various PMC masters, the TSI-148, and the i7. Because the VMEbus cannot be
retried, all VMEbus slave cycles must be allowed to be processed. This becomes a problem when an i7®
cycle to the PCI slave image is in progress while a VMEbus slave cycle to the onboard DRAM is in progress.
The i7® cycle will not give up the PCI bus and the VMEbus slave cycle will not give up the VMEbus thus the
XVME-6300 becomes deadlocked. If the XVME-6300 is to be used as a master and a slave at the same time,
the VMEbus master cycles must obtain the VMEbus prior to initiating VMEbus cycles.
All Slave interface cycles are byte swapped to maintain address coherency.
