XVME-6300
6U VME Intel i7 Core Processor Board
Acromag, Inc. Tel: 248-295-0310
- 25 -
www.acromag.com
System Resources
The XVME-6300 automatically provides slot 1 system resource functions (also referenced as SysCon) if the
Bus Grant 3 jumpers are set correctly on the VMEbus backplane. The system resource functions are
explained in the TSI-148 manual. (Contact Tundra at www.tundra.com for a PDF version of the TSI-148
manual.) This function can be disabled using the XVME-6300’s SW1 switch. See Switch Settings in Chapter 2
(p.12).
VMEbus Master Interface
The XVME-6300 can be either a VMEbus master by accessing a PCI slave channel or the DMA channel
initiates a transaction. There are 8 PCI slave images. The first PCI slave image has a 4K resolution the other
have 64K resolution. The master can generate A16, A24 and A32 VMEbus cycles for each PCI slave image.
The address mode and type are also programmed on a PCI slave image basis. The PCI memory address
location for the VMEbus master cycle is specified by the Base and Bound address. The VME address is
calculated by adding the Base address to the Translation offset address. All PCI slave images are located in
the PCI bus Memory Space. The master cycles are all byte swapped maintaining address coherency.
Caution: PCI slave images mapped to a system DRAM area will access the system DRAM not the PCI slave
image. Also the TSI-148 configuration register has a higher priority than the PCI slave images. This means
if the PCI slave image and the TSI-148 configuration registers are mapped in to the same memory area the
configuration registers will take precedence.
VMEbus Slave Interface
The XVME-6300 can be either a VMEbus slave by being accessing a VMEbus slave image or the DMA channel
initiates a transaction. There are eight PCI slave images. The first slave image has a 4K resolution the others
(2-4, 6-8) have 64K resolution. Slave images 1-8 have been implemented on the XVME-6300. The slave can
respond to A16, A24 and A32 VMEbus cycles for each VMEbus slave image. The address mode and type are
also programmed on a VMEbus slave image basis. The VMEbus memory address location for the VMEbus
slave cycle is specified by the Base and Bound address. The PCI address is calculated by adding the Base
address to the Translation offset address.
The XVME-6300 DRAM memory is based on the PC/AT architecture and is not contiguous. The VMEbus
Slave Images may be setup to allow this DRAM to appear as one Contiguous block. The first VMEbus slave
Image must have Base and Bound register set to 640K.
(Example: VMEbus Slave Image 0 BS= 0000000hBD= A0000hTO = 0000000h)
The second VMEbus Slave Image must have the Base register set to be contiguous with the
Bound register from the first VMEbus Slave Image. The Bound register is limited by the
Total XVME-6300 DRAM. The Translation Offset register is offset by 384K which is
equivalent to the A0000h-FFFFFh range on the XVME-6300 board.
