S
E
RIE
S
P
MC34
1 P
CI ME
Z
Z
A
NINE
CA
RD
S
IMUL
T
A
NE
O
US
A
NA
LO
G
INP
UT
MOD
ULE
___________
________________________________________________________________________________
- 22
-
DATA
I/O
INTERFACE
SERIAL TO PARALLEL
AMP
INST.
S/H & ADC
CH0 & CH8
INTERRUPT
AMP
INST.
REGISTERS
REGISTER
HIGH BANK TIMER
LOW BANK TIMER
LOGIC
COMMON
FPGA
PCI LOGIC
J1/J2
PMC341 BLOCK DIAGRAM
8501-878A
INPUT
MUX
DATA
P1
PRECISION
CALIBRATION
VOLTAGES
CONTROL
LOGIC
CONVERTER
PCI BUS
S/H & ADC
CH7 & CH15
THRESHOLD
MEMORY
BUFFER 2
512 SAMPLES
CHANNEL ENABLE
CONTROL
REGISTER
INTERRUPT
ANALOG
INTERFACE
ANALOG
INPUT
CHANNELS
EXTERNAL TRIGGER INPUT OR OUTPUT
MEMORY
BUFFER 1
512 SAMPLES
