SERIES PMC341 PCI MEZZANINE CARD SIMULTANEOUS ANALOG INPUT MODULE
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be programmed with a delay. If this register is left as zero
erroneous operation will result.
The 24-bit High Bank Timer value is divided by an 8 MHz
clock signal. The output of this Timer is used to precisely
generate periodic trigger pulses to control the frequency at which
the bank of channels 8 to 15 are simultaneously converted. The
time period between trigger pulses is described by the following
equation:
High Bank Timer Value + 1
= T in seconds
8 000 000
,
,
Hz
Where:
T
= the desired time period between trigger pulses in seconds.
The
High Bank Timer Value
can be minimum of 63 decimal.
The maximum value is 16,777,150 decimal.
The maximum period of time which can be programmed to
occur between conversions is (16,777,150 + 1)
8,000,000 =
2.097143875 seconds. The minimum time interval which can be
programmed to occur is (63 + 1)
8,000,000 = 8.0
seconds.
This minimum of 8.0
seconds is defined by the minimum
conversion time of the hardware. This gives channels 0 to 7 eight
micro seconds to complete their simultaneous conversion. Then,
channels 8 to 15 can be simultaneously converted.
Reading or writing the High Bank Timer register is possible
with 32-bit, 16-bit or 8-
bit data transfers. This register’s contents
are cleared upon reset.
Memory Threshold Register (Read/Write, 14H)
The Memory Threshold register is an 8-bit register that is
used to control transition between two 512 deep memory banks.
One memory bank is used to store converted analog input data
while the other is accessible for reading of converted analog input
data. When the analog input memory buffer contains more
samples than the Memory Threshold value the memory banks will
switch. This allows software to read the new converted analog
input data. The new data must be read before the memory banks
switch again. If the system cannot keep up by reading the
memory buffer before they switch, then the automatic disabling of
analog input upon memory bank switching can be selected via
the control register bit-6.
The number of valid analog input data samples available in
the memory buffer will be one more than the value set in the
Memory Threshold register. Thus, if the memory threshold value
is 33 then 34 valid data entries will be present in memory when
the memory buffer switch occurs. The Memory Threshold
register value can be any value between 1 and 511.
An interrupt can also be issued upon exceeding the specified
threshold level, if enabled via bit-0 of the interrupt register. This
interrupt indicates that new data is available in the memory
buffer. An interrupt request can be released by setting bit-15 of
the Interrupt register to a logic one. The interrupt request can
also be disabled by setting bit-0 to a logic zero; however, the
interrupt request will remain active on the PMC341 until released
via bit-15.
Reading or writing to this register is possible via 32-bit, 16-bit
or 8-bit data transfers. This regis
ter’s contents are set to 1FF hex
(511 decimal) upon reset.
Start Convert Register (Write Only, 18H)
The Start Convert register is write-only and is used to trigger
conversions by setting data bit-0 to a logic one. This method of
starting conversions is most useful for its simplicity and for when
precise time of conversion is not critical. Typically, software
triggering is used for initiating the first conversion. The PMC341
control and timer register bits must first be configured before the
Start Convert bit is set.
This register can be written via 32-bit, 16-bit or 8-bit data
transfer. Data bit-0 must be a logic one to initiate data
conversions.
Start Convert Register
Not Used
Start Convert
31
01
00
Memory Buffer (Read Only, 800H to FFCH)
In order to support burst data acquisition of digitized
converted data, two 512-sample memory buffers are used. While
one buffer functions to acquire new data input from the
converters, the other functions as a read buffer. Data can be
read at burst rates via the PCI bus to obtain new digitized data.
The two memory buffers switch functions based upon the
Memory Threshold register value, when the number of new input
digitized data samples exceeds the Memory Threshold value.
Since all channels share the same memory, channel data
tagging is implemented. The tag value identifies the channel to
which the data corresponds. The hardware tags each memory
location with a channel number, so the data can easily match with
its source channel.
The Memory samples are 20-bit data values. The least
significant bits, 15 to 0, represent the digitized data while bits 19
to 16 represent the channel tag.
Care should be taken when reading data from the memory
buffer. To insure the memory buffer data is valid the Transition
Status bit (bit-8 of the Control Register) can be polled. The
Transition Status bit will be set when valid data is available in the
memory buffer. The Transition Status bit is cleared upon the first
read of the memory buffer and will not be set again until the
memory buffers switch, based upon the Threshold register value.
Alternatively, an interrupt upon threshold met condition can be
used to start reading of valid data.
Reading of the Memory is possible via 32-bit, 16-bit, or 8-bit
data transfers.
Analog Input and Corresponding Digital Codes
The data coding is in binary two’s compliment. The digital
code corresponding to each of the given ideal analog input values
is given in binary two’s complement format in Table 3.5. Note
that the 14 bit data values are left justified within the 16-bit word.
For the PMC341 the least significant 2 bits will be returned as
zero when read.
