SERIES IP320 INDUSTRIAL I/O PACK 12-BIT HIGH DENSITY ANALOG INPUT BOARD
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Uncalibrated Performance
The uncalibrated performance is affected by two primary error
sources. These are the Programmable Gain Amplifier (PGA) and
the Analog to Digital Converter (ADC). The untrimmed PGA and
ADC have the following performance:
PGA203KP @25oC:
Linearity Error is
±
0.012% Maximum (i.e. 1/2-LSB).
Offset Error RTI is
±
(0.5mV + 5/Gain) Typical;
±
(2mV + 24/Gain) Maximum. This is summarized as:
PGA Gain
Max Offset
Error RTI (mV)
Max Offset
Error RTO (mV)
1
26
26
2
14
28
4
8
32
8
5
40
Gain Error is 0.05% typical, 0.25% maximum for all gains xxxxx.
(ADC) ADS774KE @25oC:
Linearity Error is
±
0.5 LSB Maximum.
Unipolar Offset Error is
±
2 LSB Maximum.
Bipolar Offset Error is
±
4 LSB Maximum.
Full Scale Calibration Error is
±
0.25% of span, Maximum.
Table 3.3 summarizes the maximum uncalibrated error
combining the PGA and the ADC errors:
Table 3.3: Maximum Overall Uncalibrated Error
Input Range
(Volts)
PGA
Gain
ADC
Range
(Volts)
Max
Offset
Error
(
±±±±
LSB)
Max
Gain
Error
(
±±±±
LSB)
-5 to +5
1
-5 to +5
14.7
15.4
-2.5 to +2.5
2
"
15.5
"
-1.25 to +1.25
4
"
17.1
"
-0.625 to +0.625
8
"
20.4
"
-10 to +10
1
-10 to +10
9.3
"
-5 to +5
2
"
9.7
"
-2.5 to +2.5
4
"
10.6
"
-1.25 to +1.25
8
"
12.2
"
0 to +10
1
0 to +10
12.7
20.5
0 to +5
2
"
13.5
"
0 to +2.5
4
"
15.1
"
0 to +1.25
8
"
18.4
"
Note that the worst case non-linearity error is
±
1 LSB (the sum
of the 1/2-LSB non-linearities of the PGA and ADC).
Calibrated Performance
Very accurate calibration of the IP320 can be accomplished by
using calibration voltages present on the board. The four voltages
and the analog ground reference are used to determine the
endpoints of a straight line which defines the analog input
characteristic. The calibration voltages are precisely adjusted at the
factory to provide optimum performance, as detailed in the following
table:
Calibration
Signal
Ideal
Value
(Volts)
Maximum
Tolerance
@25oC (Volts)
Maximum
Temperature
Drift (ppm/oC)
Auto Zero
0.0000
±
0.0002
0
CAL0
4.9000
±
0.0005
±
15
CAL1
2.4500
±
0.0005
±
20*
CAL2
1.2250
±
0.0004
"
CAL3
0.6125
±
0.0002
"
* Worst case temperature drift is the sum of the
±
15 ppm/oC drift of
the calibration voltage reference plus the
±
5 ppm/oC drift of the
resistors in the voltage divider.
The calibration voltages are used with the auto zero signal to
find two points that determine the straight line characteristic of the
analog front end for a particular range. The recommended
calibration voltage selection for each range is summarized in the
following table:
Table 3.4: Recommended Calib. Voltages For Input Ranges
Input
Range
(Volts)
PGA
Gain
ADC
Range
(Volts)
Rec. Low
Calib. Voltage
"VoltCALLO"
(Volts)
Rec. High
Calib. Voltage
"VoltCALHI"
(Volts)
-5 to
+5
1
-5 to
+5
0.0000 (A. Z.)
4.9000 (CAL0)
-2.5 to
+2.5
2
"
"
2.4500 (CAL1)
-1.25 to
+1.25
4
"
"
1.2250 (CAL2)
-0.625 to
+0.625
8
"
"
0.6125 (CAL3)
-10 to
+10
1
-10 to
+10
"
4.9000 (CAL0)
-5 to
+5
2
"
"
4.9000 (CAL0)
-2.5 to
+2.5
4
"
"
2.4500 (CAL1)
-1.25 to
+1.25
8
"
"
1.2250 (CAL2)
0 to
+10
1
0 to
+10
0.6125 (CAL3)
4.9000 (CAL0)
0 to
+5
2
"
"
4.9000 (CAL0)
0 to
+2.5
4
"
"
2.4500 (CAL1)
0 to
+1.25
8
"
"
1.2250 (CAL2)
The following equation (1) is used to correct the actual ADC
data (i.e. the uncorrected bit count read from the ADC) making use
of the calibration voltages and range constants.
Corrected_Count = [ ( 4096 * m ) / Ideal_Volt_Span ] *
[ Count_ ( ( VoltCALLO * Gain ) - Ideal_Zero ) / m -
CountCALLO ] (1)
where, "m" represents the actual slope of the transfer characteristic
as defined in equation 2:
