Acromag IP236 Series, User Manual, Page: 8 / 26

SERIES IP236 INDUSTRIAL I/O PACK FIFO BUFFERED 16 BIT ANALOG OUTPUT MODULE
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Hex
Base
Adr+ MSB
D15 D08
LSB
D07 D00
Hex
Base
Adr+
26 Timer Prescaler
3
Channel 5
Control/Status
Channel 5
27
28 Conversion Timer
3
Channel 5
29
2A FIFO Port Channel 5
3
2B
2C
Timer Prescaler
3
Channel 6
Control/Status
Channel 6
2D
2E Conversion Timer
3
Channel 6
2F
30 FIFO Port Channel 6
3
31
32 Timer Prescaler
3
Channel 7
Control/Status
Channel 7
33
34 Conversion Timer
3
Channel 7
35
36 FIFO Port Channel 7
3
37
38
Reserved
4
Not Used
1
39
3A Not Used
1
⇓
3B
7E Not Used
1
7F
Notes (Table 3.2):
1. The IP will not respond to addresses that are "Not Used".
2. All Reads and writes are 0 wait states (except write to FIFO
ports which require 2 wait states typically).
3. Channels 4-7 are only present on 8 channel models.
4. This byte is reserved for use at the factory to enable writing of
the calibration coefficients.
Channel Software Reset Register (Write Only, 00H)
This is a write only register that allows software reset on an
individual channel basis. Setting data bits 8 to 15 will issue a
software reset to the individual channels per the table below. The
software reset will clear the individual channel’s control register,
counters, and FIFO buffer.
Channel Software Reset Register
MSB LSB
15 14 13 12 11 10 09 08
Ch7 Ch6 Ch5 Ch4 Ch3 Ch2 Ch1 Ch0
Start Convert & FIFO Full Status Register (Read/Write, 01H)
The Start Convert register (bits-7 to 0) is used to start the
conversions of the individual channels. When the channel’s
corresponding bit is set high, per the table below, conversions are
initiated for that channel. The desired mode of conversion must
first be configured by setting the channel’s: Control, Timer
Prescaler, Conversion Timer, and FIFO buffer. Note, if interrupts
are used the interrupt vector must also be set prior to issue of a
software start convert.
When External Trigger Only mode is selected via bits 2 and 1
of the channel’s control register (set to “11”), the channel
Software Start Convert bit is disabled from starting data
conversions.
This register can be written with either a 16-bit or 8-bit data
value. The channel’s actual conversion will be initiated 6.625
µ
seconds after setting its corresponding Start Convert Bit.
Start Convert & FIFO Full Status Register
MSB LSB
07 06 05 04 03 02 01 00
Ch7 Ch6 Ch5 Ch4 Ch3 Ch2 Ch1 Ch0
When read this register is used to reflect the FIFO full status
of the individual channel FIFO buffers. The individual bits used to
indicate FIFO Full status for each of the channel FIFOs is shown
in the previous table. A set bit indicates that the channel’s FIFO
is full. No additional writes to the FIFO buffer should be
implemented after the FIFO is full since data transfer will not be
acknowledged and can result in a system bus error.
This register can be read as either a 16-bit or 8-bit data read.
FIFO Full status will be cleared upon software or hardware reset.
Interrupt Status Register (Read Only, 02H)
The Interrupt Status register (bits 15 to 8) represents the
interrupt status of each of the analog output channels. A set bit
represents an active interrupt request for the corresponding
channel. Disabling a channel interrupt enable bit will clear its
interrupt status bit. The interrupt status bit corresponding to each
of the analog output channels is shown in the following table.
The interrupt status bits are read only bits and can be read as
either 8 or 16-bit values.
Interrupt Status Register
MSB LSB
15 14 13 12 11 10 09 08
Ch7 Ch6 Ch5 Ch4 Ch3 Ch2 Ch1 Ch0
Interrupt Vector Register (Read/Write, 03H)
The Vector Register can be written with an 8-bit interrupt
vector. This vector is provided to the carrier and system bus
upon an active INTSEL* cycle. Reading or writing to this register
is possible via 16-bit or 8-bit data transfers.
Interrupt Vector Register
MSB LSB
07 06 05 04 03 02 01 00
The IP236 Interrupt Vector register can be used as a pointer
to an interrupt handling routine. The vector is an 8-bit value and
can be used to point to any one of 256 possible locations to
access the interrupt handling routine.
An interrupt can be enabled for generation when the number
of samples in the FIFO is equal to or less than the set threshold
(see the Channel Control register section). Interrupts generated
by the IP236 use interrupt request line INTREQ0* (Interrupt
Request 0). The IP236 will release the INTREQ0* signal after the
FIFO buffer has more samples than the set threshold or if
interrupts are disabled.
Issue of a hardware reset will clear the contents of this
register to 0. A software reset has no effect on this register.