SERIES IP236 INDUSTRIAL I/O PACK FIFO BUFFERED 16 BIT ANALOG OUTPUT MODULE
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CHANNEL REGISTERS
Each channel has it own control/status, counters, and FIFO
Buffer registers. This allows each channel to function
independently of all others in the module. These registers
include a control/status register, 8-bit Timer Prescaler, 16-bit
Conversion Timer, and FIFO Port register. Each of these
registers are described in the following sections.
Channel Control & Status Register (Read/Write)
This 8-bit read/write register is used to: enable single or
continuous conversions, control external trigger mode, enable
interrupts, set the FIFO interrupt threshold, and identify a FIFO
almost empty condition.
The function of each of the control register bits are described
in Table 3.4. This register can be read or written with either 8-bit
or 16-bit data transfers. A power-up or software channel reset
sets all control register bits to 0.
Table 3.4: Channel Control/Status Register
BIT
FUNCTION
0
Status
Bit
0 = FIFO is not almost empty
1 = FIFO is almost empty. This bit is set to a
logic 1 when the channel’s FIFO contains
less than or equal to the number of data
samples set by the threshold bits (6 and 5).
2, 1
00 = Conversions are disabled.
01 = Enable Single Conversion Mode. A single
conversion is initiated per software start
convert or external trigger. The internal
channel timer has no function in this mode of
operation.
10 = Enable Continuous Conversion Mode.
Conversions are initiated by a software start
convert or external trigger and continued by
internal hardware triggers generated at the
frequency set by the interval timer registers.
11 = External Trigger Input Mode. Conversions
are initiated only by external triggers in this
mode of operation. The software start
convert and internal hardware generated
triggers do not initiate conversions in this
mode of operation.
3
0 = External Trigger Set as Input
1 = External Trigger Set as Output. As an output
Internal Timer triggers are driven on the
External trigger pin of the field I/O connector.
It is possible to synchronize the conversion of
multiple IP236 modules. A single master
IP236 must be selected to output the external
trigger signal while all other modules are
selected to input the external trigger signal.
The external trigger signals (pins 49 to 42 of
the field I/O connector) of all modules must
be wired together for all channels/modules to
be synchronized.
The External Trigger input can be
sensitive to external EMI noise which can
cause erroneous external triggers. If
External Trigger Inputs are not required, the
External Trigger should be configured as an
output.
BIT
FUNCTION
4
0 = Disable Interrupt
1 = Enable Interrupt
An interrupt request from the IP236 will be
issued to the system if enabled via this bit and
the FIFO has equal to or less than the
threshold number of bytes selected via bits 6
and 5. The interrupt request will remain active
until the interrupt condition is removed by
writing new data to the FIFO buffer (thus
moving the number of values above the set
threshold) or by disabling interrupts via this bit.
6, 5
FIFO Interrupt Threshold
00 = Disabled no Threshold Set
01 = Threshold of 4 samples selected.
10 = Threshold of 16 samples selected.
11 = Threshold of 64 samples selected.
When the data samples in the corresponding
FIFO is equal to or falls below the selected
threshold an interrupt request can be issued
and the FIFO Almost Empty bit-0 of this
register will be set. Note: Interrupts must also
be enabled on the carrier and via bit 4 of this
register.
7
Not Used
Channel Timer Prescaler Register (Read/Write)
The Channel Timer Prescaler register is an 8-bit register that
can be written with an 8-bit or 16-bit data transfer to control the
interval time between conversions.
Timer Prescaler Register
MSB Data Bus LSB
15
14
13
12
11
10
09
08
MSB Timer Prescaler Value LSB
07
06
05
04
03
02
01
00
This 8-bit number divides the 8 MHz clock signal. The clock
signal is further divided by the number held in the Conversion
Timer Register. The resulting frequency can be used to generate
periodic triggers for precisely timed intervals between
conversions.
The Timer Prescaler has a minimum allowed value
restriction of 35 hex or 53 decimal.
A Timer Prescaler value of
less then 53 (decimal) will result in unpredictable operation. This
minimum value corresponds to a conversion interval of 6.625
µ
seconds which translates to the maximum conversion rate of
about 150KHz. Although the board will operate at the 150KHz
conversion rate, conversion accuracy will be sacrificed. To
achieve specified conversion accuracy a maximum conversion
rate of 100KHz is recommended (see the specification chapter
for details regarding accuracy).
The formula used to calculate and determine the desired
Timer Prescaler value is given in the Conversion Timer section
which immediately follows.
Reading or writing to this register is possible via 16-bit or 8-bit
data transfers. The Timer Prescaler register contents are cleared
upon reset.