Acromag IP236 Series User Manual Download Page 7

SERIES IP236 INDUSTRIAL I/O PACK                           FIFO BUFFERED 16 BIT ANALOG OUTPUT MODULE 
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3.0   PROGRAMMING INFORMATION

 

 
ADDRESS MAPS

 

 

This manual is presented using the “Big Endian” byte 

ordering format.  Big Endian is the convention used in the 
Motorola 68000 microprocessor family and is the VMEbus 
convention.  In Big Endian, the lower-order byte is stored at odd-
byte addresses.  Thus, byte accesses are done on odd address 
locations.  The Intel x86 family of microprocessors use the 
opposite convention, or “Little Endian” byte ordering.  Little 
Endian uses even-byte addresses to store the low-order byte.  As 
such, use of this module on a PC carrier board will require the 
use of the even address locations to access the 8-bit data, while 
a VMEbus carrier requires the use of odd address locations. 

 

IDENTIFICATION SPACE - (Read Only, 32 Odd-Byte 
Addresses)

 

 

Each IP module contains identification (ID) information that 

resides in the ID space per the IP module specification.  This 
area of memory contains 32 bytes of information at most.  Both 
fixed and variable information may be present within the ID 
space.  Fixed information includes the "IPAC" identifier, model 
number, and manufacturer's identification codes.  Variable 
information includes unique information required for the module.  
The IP236 ID information space does not contain any variable 
(e.g. unique calibration) information.  ID space bytes are 
addressed using only the odd addresses in a 64 byte block (on 
the “Big Endian” VMEbus).  Even addresses are used on the 
“Little Endian” PC ISA bus and PCI bus.  The IP236 ID space 
contents are shown in Table 3.1.  Note that the base-address for 
the IP module ID space (see your carrier board instructions) must 
be added to the addresses shown to properly access the ID 
space.  Execution of an ID space read requires 0 wait states. 
 

Table 3.1: IP236 ID Space Identification (Format I)  

Hex Offset 

From ID 

Base 

Address 

 

ASCII 

Character  

Equivalent 

 

Numeric 

 Value 

 (Hex) 

 
 
 

Field Description 

01 

49 

All IP's have 

'IPAC' 

03 

50 

 

05 

41 

 

07 

43 

 

09 

 

A3 

Acromag ID Code 

0B 

 

(26 

IP236-8) 

(27 

IP236-4)  

IP Model Code

1

  

0D 

 

00 

Not Used 

(Revision) 

0F 

 

00 

Reserved 

11 

 

00 

Not Used (Driver 

ID Low Byte) 

13 

 

00 

Not Used (Driver 

ID High Byte) 

15 

 

0C 

Total Number of 

ID PROM Bytes 

17 

 

(93 

IP236-8) 

(F2 

IP236-4)  

CRC 

19 to 3F 

 

yy 

Not Used 

 
Notes (Table 3.1):

 

1.   The IP model number is represented by a two-digit code 

within the ID space (for example the IP236-8 model is 
represented by 26 Hex). 

 
I/O SPACE ADDRESS MAP

 

 

This board is addressable in the Industrial Pack I/O space to 

control the conversion of analog outputs to the field.  As such, 
three types of information are stored in the I/O space: control, 
status, and data. 

 
The I/O space may be as large as 64, 16-bit words (128 

bytes) using address lines A1 to A6, but the IP236 uses only a 
portion of this space.  The I/O space address map for the IP236 
is shown in Table 3.2.  Note that the base address for the IP 
module I/O space (see your carrier board instructions) must be 
added to the addresses shown to properly access the I/O space.  

 
Table 3.2:  IP236 I/O Space Address Memory Map

2

 

Hex
Base 
Adr+ 

MSB 

D15                   D08

 

LSB 

D07                  D00 

Hex 
Base 
Adr+ 

00 

Channel Software 

Reset 

Start Convert & 

FIFO Full Status 

 
01 

02 

Interrupt Status 

Interrupt Vector 

 
03 

04 

Rd 

Wr~

 

Calibration 
Coefficient 

Address

 

Calibration 

Coefficient Write 

Data

 

 
05 

06 

Calibration 

Coefficient Read 

Data 

 

Wr 

Busy 

Rd 

Comp 

 
07 

08 

Timer Prescaler 

Channel 0

 

Control/Status 

Channel 0 

 

 
09 

0A 

Conversion Timer 

Channel 0

 

 
0B 

0C 

FIFO Port Channel 0 

 
0D 

0E 

Timer Prescaler 

Channel 1

 

Control/Status 

Channel 1 

 

 
0F 

10 

Conversion Timer 

Channel 1

 

 
11 

12 

FIFO Port Channel1 

 
13 

14 

Timer Prescaler 

Channel 2

 

Control/Status 

Channel 2 

 

 
15 

16 

Conversion Timer 

Channel 2

 

 
17 

18 

FIFO Port Channel 2 

 
19 

1A 

Timer Prescaler 

Channel 3

 

Control/Status 

Channel 3 

 

 
1B 

1C 

Conversion Timer 

Channel 3

 

 
1D 

1E 

FIFO Port Channel 3 

 
1F 

20 

Timer Prescaler

3

 

Channel 4

 

Control/Status 

Channel 4 

 

 
21 

22 

Conversion Timer

3

 

Channel 4

 

 
23 

24 

FIFO Port Channel 4

3

 

 
25 

 
 
 

 

 

Summary of Contents for IP236 Series

Page 1: ...Module USER S MANUAL ACROMAG INCORPORATED 30765 South Wixom Road P O BOX 437 Wixom MI 48393 7037 U S A Tel 248 295 0310 Fax 248 624 9234 Copyright 1999 Acromag Inc Printed in the USA Data and specific...

Page 2: ...IP INTERFACE LOGIC 14 CONVERSION CONTROL LOGIC 15 DATA TRANSFER FROM FPGA TO DACs 15 INTERVAL TIMER 15 EXTERNAL TRIGGER 15 INTERRUPT CONTROL LOGIC 15 CALIBRATION MEMORY CONTROL LOGIC 15 5 0 SERVICE A...

Page 3: ...Ranges When the module s jumpers are set for bipolar operation the analog outputs are reset to 0 volts upon power up or receipt of a software or hardware reset This eliminates the problem of applying...

Page 4: ...ODULE VxWORKS SOFTWARE Acromag provides a software product sold separately consisting of IP module VxWorks drivers This software Model IPSW API VXW MSDOS format is composed of VxWorks real time operat...

Page 5: ...on of output voltage span The configuration of the jumpers for the different ranges is shown in Table 2 2 ON means that the pins are shorted together with a shorting clip OFF means that the clip has b...

Page 6: ...nd grounding connections External Trigger Input Output Signals The external trigger signals on pins 42 to 49 of the P2 connector can be programmed to accept a TTL compatible external trigger input sig...

Page 7: ...D Space Identification Format I Hex Offset From ID Base Address ASCII Character Equivalent Numeric Value Hex Field Description 01 I 49 All IP s have IPAC 03 P 50 05 A 41 07 C 43 09 A3 Acromag ID Code...

Page 8: ...tiated 6 625 seconds after setting its corresponding Start Convert Bit Start Convert FIFO Full Status Register MSB LSB 07 06 05 04 03 02 01 00 Ch7 Ch6 Ch5 Ch4 Ch3 Ch2 Ch1 Ch0 When read this register i...

Page 9: ...ibration Coefficient Status register is a read only register and is used to access the calibration coefficient read data and determine the status of a read cycle initiated by the Calibration Coefficie...

Page 10: ...e wired together for all channels modules to be synchronized The External Trigger input can be sensitive to external EMI noise which can cause erroneous external triggers If External Trigger Inputs ar...

Page 11: ...ardware reset It is recommended that interrupts be enabled for a FIFO almost empty condition 64 16 or 4 samples or less left in the FIFO Upon this interrupt no more then 128 samples minus the threshol...

Page 12: ...board documentation for compatibility details 1 Clear the global interrupt enable bit in the carrier board status register by writing a 0 to bit 3 2 Write the interrupt vector to the IP236 Module at...

Page 13: ...o the DAC channel to accurately generate the desired output voltage See the specification chapter for details regarding maximum calibrated error Data is corrected using a couple of formulas Equation 1...

Page 14: ...value is rounded to 8 197 and is equivalent to DFFB hex as a 2 s complement value 6 Execute Write of DFFB hex to the Channel 0 s FIFO Buffer port at Base Address 0CH 7 Execute Write of 0001H to the S...

Page 15: ...rnal trigger input is enabled via bit 3 of the channel s control register the falling edge of the external trigger will initiate conversions for the corresponding channel For External Trigger Input mo...

Page 16: ...econds Power IP236 Requirements 8 8E 4 4E 5V Typical 92mA 50mA 5 Max 120mA 65mA 12V Typical 130mA 65mA 5 Max 170mA 85mA 12V Typical 160mA 82mA 5 Max 210mA 115mA ENVIRONMENTAL Operating Temperature Sta...

Page 17: ...Bipolar Offset Error is 0 2 FSR i e 20V SPAN max Gain Error is 0 25 maximum Settling Time 10uS to within 0 003 of FSR for a 20V step change load of 5K in parallel with 500pF Conversion Rate per channe...

Page 18: ...ndustrial I O Pack IP Each Industrial I O Pack IP has its own unique P2 pin assignments Refer to the IP module manual for correct wiring connections to the termination panel Schematic and Physical Att...

Page 19: ...TIGHTEN 4 PLACES THE RECOMMENDED TORQUE IS 0 226 NEWTON METER OR 2 INCH POUNDS OVER TIGHTENING MAY DAMAGE CIRCUIT BOARD 2 INSERT FLAT HEAD SCREWS ITEM A THROUGH SOLDER SIDE OF IP MODULE AND INTO HEX S...

Page 20: ...SERIES IP236 INDUSTRIAL I O PACK FIFO BUFFERED 16 BIT ANALOG OUTPUT MODULE ___________________________________________________________________________________________ 20...

Page 21: ...SERIES IP236 INDUSTRIAL I O PACK FIFO BUFFERED 16 BIT ANALOG OUTPUT MODULE ___________________________________________________________________________________________ 21...

Page 22: ...SERIES IP236 INDUSTRIAL I O PACK FIFO BUFFERED 16 BIT ANALOG OUTPUT MODULE ___________________________________________________________________________________________ 22...

Page 23: ...SERIES IP236 INDUSTRIAL I O PACK FIFO BUFFERED 16 BIT ANALOG OUTPUT MODULE ___________________________________________________________________________________________ 23...

Page 24: ...SERIES IP236 INDUSTRIAL I O PACK FIFO BUFFERED 16 BIT ANALOG OUTPUT MODULE ___________________________________________________________________________________________ 24...

Page 25: ...SERIES IP236 INDUSTRIAL I O PACK FIFO BUFFERED 16 BIT ANALOG OUTPUT MODULE ___________________________________________________________________________________________ 25...

Page 26: ...SERIES IP236 INDUSTRIAL I O PACK FIFO BUFFERED 16 BIT ANALOG OUTPUT MODULE ___________________________________________________________________________________________ 26...

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