Acromag AVME9630 Series User Manual Download Page 7

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INDUSTRIAL I/O PACK SERIES AVME9630/9660 VMEbus 3U/6U CARRIER BOARDS
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TABLE 2.3: VMEbus P1 CONNECTIONS

Pin Description Pin Description Pin Description

1A D00

BBSY*

D08

2A D01

BCLR*

D09

3A D02

ACFAIL*

D10

4A D03

BG0IN*

4C D11

5A D04

BG0OUT*

5C D12

6A D05

BG1IN*

6C D13

7A D06

BG1OUT*

7C D14

8A D07

BG2IN*

8C D15

9A GND

BG2OUT*

9C GND

10A SYSCLK 10B BG3IN* 10C

SYSFAIL*

11A GND 11B

BG3OUT*

11C

BERR*

12A DS1* 12B

BR0*

12C

SYSRESET*

13A DS0* 13B

BR1*

13C

LWORD*

14A WRITE* 14B

BR2*

14C AM5

15A GND 15B

BR3*

15C A23

16A DTACK* 16B AM0 16C

A22

17A GND 17B AM1 17C  A21
18A AS* 18B AM2 18C A20
19A GND 19B AM3 19C  A19
20A IACK* 20B  GND  20C  A18
21A IACKIN* 21B

SERCLK

21C

A17

22A IACKOUT* 22B

SERDAT*

22C

A16

23A AM4 23B GND 23C A15
24A A07 24B

IRQ7*

24C A14

25A A06 25B

IRQ6*

25C A13

26A A05 26B

IRQ5*

26C A12

27A A04 27B

IRQ4*

27C A11

28A A03 28B

IRQ3*

28C A10

29A A02 29B

IRQ2*

29C A09

30A A01 30B

IRQ1*

30C A08

31A -12V 31B

5V STDBY

31C

+12V

32A +5V 32B +5V 32C +5V

Asterisk (*) is used to indicate an active-low signal.

BOLD ITALIC

Logic Lines are NOT USED by the carrier board.

POWER-UP TIMING AND LOADING

The AVME9630/9660 boards use a Field Programmable Gate-

Array (FPGA) to handle the bus interface and control logic timing.
Upon power-up, the FPGA automatically clocks in configuration
vectors from a local PROM to initialize the logic circuitry for normal
operation. This time is measured as the first 145mS (typical) after
the +5 Volt supply rises to +2.5 Volts at power-up. The VMEbus
specification requires that the bus master drive the system reset for
the first 200mS after power-up, thus inhibiting any data transfers
from taking place.

IP control registers are also reset following a power-up

sequence, disabling interrupts, etc. (see Section 3 for details).

DATA TRANSFER TIMING

VMEbus data transfer time is measured from the falling edge

of DSx* to the falling edge of DTACK* during a normal data
transfer cycle. Typical transfer times are given in the following
table.

Register

Data Transfer Time

All Carrier Registers

500 nS, Typical.

IP Registers

750 nS, Typical, If No Wait
States*

* See IP module specifications for information on wait states. IP

module register access time will increase by the number of wait
states multiplied by 125nS (the period of the 8 MHz clock).

FIELD GROUNDING CONSIDERATIONS

Carrier boards are designed with passive filters on each supply

line to each IP module. This provides maximum filtering and signal
isolation between the IP modules and the carrier board. However,
the boards are considered non-isolated, since there is electrical
continuity between the VMEbus and the IP grounds. Therefore,
unless isolation is provided on the IP module itself, the field I/O
connections are not isolated from the VMEbus. Care should be
taken in designing installations without isolation to avoid ground
loops and noise pickup. This is particularly important for analog
I/O applications when a high level of accuracy/resolution is needed
(12-bits or more). Contact your Acromag representative for
information on our many isolated signal conditioning products that
could be used to interface to the IP input/output modules.

3.0 PROGRAMMING INFORMATION

This Section provides the specific information necessary to

operate the AVME9630/9660 non-intelligent carrier boards.

The board is addressable on 1K byte boundaries in the Short

I/O (A16) Address Space. This Acromag VMEbus non-intelligent
slave (carrier board) has a Board Status register, but no ID PROM.
ID PROM’s are provided per the Industrial I/O Pack logic interface
specification on the mezzanine (IP) boards which are installed on
the carrier. The 1K byte of memory consumed by the board is
composed of blocks of memory for the I/O and ID spaces of up to
four IP modules. The rest of the 1K byte address space is unused,
or contains registers or memory specific to the function of the
carrier board. The memory map for AVME9630 and AVME9660
are shown in Tables 3.1A and 3.1B respectively. Note that the
memory maps for the two models are identical for IP modules A
and B and the control register locations. The AVME9630 does not
contain IP modules C or D.

MEMORY MAPS

Table 3.1A: AVME9630 3U Carrier Bd Short I/O Memory Map

Base
A
(Hex)

EVEN Byte

D15 D08

ODD Byte

D07 D00

Base
A
(Hex)

0000

↓

007E

IP A

I/O Space