Acromag AVME9630 Series User Manual Download Page 10

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INDUSTRIAL I/O PACK SERIES AVME9630/9660 VMEbus 3U/6U CARRIER BOARDS
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IP Error Register - (Read, Base + C5H)

The IP Error Register allows the user to monitor the Error

signals of IP modules A through D. The Industrial I/O Pack
specification states that the error signals indicate a non-
recoverable error from the IP (such as a component failure or hard-
wired configuration error). Refer to your IP specific documentation
to see if the error signal is supported and what it indicates.

MSB
D7

LSB
D0

Not
Used

IP-D
Error
*

IP-C
Error
*

IP-B
Error

IP-A
Error

* Bits not used on AVME9630 - equal “0” if read.

Where:

Bits 7, 6, 5, 4

Not used - equal "0" if read

Bit 3
IP-D Error
(Read)

This bit will be a "1" when IP D asserts its
Error signal. This bit will be “0” when there is
no error.
Reset Condition: Bit will be “0” (no error)
unless driven by IP.

Bit 2
IP-C Error
(Read)

This bit will be a "1" when IP C asserts its
Error signal. This bit will be “0” when there is
no error.
Reset Condition: Bit will be “0” (no error)
unless driven by IP.

Bit 1
IP-B Error (Read)

This bit will be a "1" when IP B asserts its
Error signal. This bit will be “0” when there is
no error.
Reset Condition: Bit will be “0” (no error)
unless driven by IP.

Bit 0
IP-A Error (Read)

This bit will be a "1" when IP A asserts its
Error signal. This bit will be “0” when there is
no error.
Reset Condition: Bit will be “0” (no error)
unless driven by IP.

IP Memory Enable Register - (Read/Write, Base + C7H)

The IP Memory Enable Register allows the user to program

which IP modules will be accessible in the standard (A24) memory
space. An enable bit is associated with each IP A through D. This
register must be used in conjunction with the IP Memory Base
Address & Size Registers to fully define the addressable memory
space of the IP modules. Enabling IP memory has no effect on the
I/O and ID spaces of the module.

MSB
D7

LSB
D0

Not
Used

IP-D
Mem
Ena*

IP-C
Mem
Ena*

IP-B
Mem
Ena

IP-A
Mem
Ena

* These Bits are Not Used on AVME9630.

Where:

Bits 7, 6, 5, 4

Not used - equal "0" if read.

Bit 3
IP-D Memory Enable
(Read/Write)

Writing a "1" to this bit enables the
memory space for IP D. A zero disables
memory space accesses.
Reset Condition: Set to "0", memory
space accesses disabled for IP D.

Bit 2
IP-C Memory Enable
(Read/Write)

Writing a "1" to this bit enables the
memory space for IP C. A zero disables
memory space accesses.
Reset Condition: Set to "0", memory
space accesses disabled for IP C.

Bit 1
IP-B Memory Enable
(Read/Write)

Writing a "1" to this bit enables the
memory space for IP B. A zero disables
memory space accesses.
Reset Condition: Set to "0", memory
space accesses disabled for IP B.

Bit 0
IP-A Memory Enable
(Read/Write)

Writing a "1" to this bit enables the
memory space for IP A. A zero disables
memory space accesses.
Reset Condition: Set to "0", memory
space accesses disabled for IP A.

IP Memory Base Address & Size Registers - (Read/Write)
IP_A (Base + D1H)
IP_B (Base + D3H)
IP_C (Base + D5H), Not used on AVME9630
IP_D (Base + D7H), Not used on AVME9630

The IP Memory Base Address & Size Registers are user

programmable to define the starting address of standard (A24)
memory space and the size of that memory space corresponding
to IP modules A through D. The memory size for each enabled IP
module is user-programmable from 1MByte to 8MByte in multiples
of two. Note that memory on IP modules can only be accessed if
enabled within the IP Memory Enable Register, and that the
memory bases for enabled IP modules must not be programmed to
overlap with each other. The size selected by these registers
should be matched to that required by the associated IP.

Base Address

Not Used

Memory Size

MSB

LSB

A23 A22 A21 A20 Not

Used

Not
Used

0 0

A23 A22 A21 Not

Used

Not
Used

0 1

A23 A22 Not

Used

Not
Used

1 0

A23 Not

Used

Not
Used

1 1

Where:

Bit 7, 6, 5, 4
IP Memory Base
Address
(Read/Write)

These bits define the memory base
address. Read and write operations are
implemented on all bits even if labeled
unused. Thus, a read operation will return
the last value written.
Reset Condition: Set to "0", memory base
address 0.

Bit 3, 2

Not used - equal "0" if read.

Bit 1, 0
IP Memory Size
(Read/Write)

These bits define the memory size selected
1MB, 2MB, 4MB, or 8MB as shown in the
previous table.
Reset Condition: Set to "0", 1MB memory
size.