SERIES AP471 ACROPACK
USER
’S MANUAL
Acromag, Inc. Tel: 248-295-0310
- 26 -
http://www.acromag.com
- 26 -
www.acromag.com
combine event sensing with the built-in debounce control circuitry to obtain
“glitch-free” edge detection of incoming signals.
To program events, determine which I/O lines are to have events enabled
and which polarity is to be detected, high-to-low level transitions (negative)
or low-to-high level transitions (positive). Set each bit to the desired polarity,
and then enable each of the event inputs to be detected. Optionally, set the
interrupt enable bit in the Interrupt Register to enable board level
interrupts. Note that all I/O event inputs are reset, set to negative events,
and disabled after a power-up or software reset has occurred.
Note that no events will be detected until enabled via the Event Enable
Registers. Further, interrupts will not be reported to the carrier board unless
the interrupt enable bit of the Interrupt Register has been set.
Debounce Control
Debounce control is built into the on-board digital FPGA employed by the
AP471. You can combine debounce with event sensing to obtain “glitch-free”
edge detection of incoming signals for all 48 channels. That is, the debounce
circuitry will automatically filter out “glitches” or transients that can occur on
received signals, for error-free edge detection and increased noise immunity.
With debounce, an incoming signal must be stable for the entire debounce
time before it is recognized by the I/O or event sense logic. Debounce is
applied to both inputs and event sense inputs.
The debounce circuitry can be configured to use the 31.25MHz internal
system clock, or a clock signal present on I/O channel 47, to determine the
debounce times (see the Debounce Clock Select register). If the debounce
clock is taken from I/O47, then the effective number of inputs is reduced to
47. If the AP471 is configured to use the 31.25MHz internal system clock
(recommended), a debounce value of 4us, 64us, 1ms, or 8ms may be
selected (see the Debounce Duration Registers). As such, an incoming signal
transition must be stable for the debounce time before it is recognized by
the I/O pin or event sense logic. A slower clock may be used to provide even
longer debounce times (this clock would have to be provided on I/O47).
Upon initialization of the debounce circuitry, be sure to delay at least the
programmed debounce time before reading any of the input channels or
event signals to ensure that the input data is valid prior to being used by the
software.
Interrupt Generation
This model provides control for generation of interrupts on change-of-state,
or positive or negative events, for all 48 channels. Interrupts are only
generated when events are enabled via the Event Enable registers. Writing
“1” to the corresponding event sense bit in the Event Pending/Clear register
will clear the event. Interrupts may be reflected internally and reported by
polling the module. Control of this line is initiated via bit 0 of the Interrupt
Enable Register.
