SERIES AP471 ACROPACK
USER
’S MANUAL
Acromag, Inc. Tel: 248-295-0310
- 20 -
http://www.acromag.com
- 20 -
www.acromag.com
Write Mask Registers (Read/Write)
(BAR0 + 0x0000 0014 – 0x0000
001C)
The Write Mask Registers are used to individually mask the ability to write
data to each of the 48 channels of this model. Writing a ‘1’ to any channel’s
corresponding bit of the Mask Register will mask that channel, from
inadvertent writes. A read of these registers will return the status of the
mask. Bit 0 of each register corresponds to the lowest numbered I/O point,
while Bit 15 corresponds to the highest numbered I/O point.
Bits 31 down to 16 of these registers are not used. On power-up reset, all
bits are set to ‘0’, allowing writes to the output channels.
Event Enable Registers (Read/Write)
(BAR0 + 0x0000 0020 –
0x0000 0028)
The Event Enable Registers provide a mask bit for each of the 48 possible
interrupt channels. A “0” bit will prevent the corresponding input channel
from detecting an event. A “1” bit will allow the corresponding input
channel to detect events as configured by the Event Type and Event Polarity
Control Registers. Bit 0 of each register corresponds to the lowest numbered
I/O point, while Bit 15 corresponds to the highest numbered I/O point.
If both an Event Sense and the board Interrupt Enable bit is set, then
interrupts can be generated.
Event Type (COS or H/L) Configuration Registers (Read/Write)
Event Polarity Control Registers (Read/Write)
(BAR0 + 0x0000 0038 –
0x0000 0040)
A write to these registers controls the polarity of the input sense event for
each channel. A “1” written to a bit in these registers will cause the
corresponding event sense input channel to flag positive events (low-to-high
transitions). A “0” will cause negative events to be sensed (high-to-low
transitions). Bit 0 of each register corresponds to the lowest numbered I/O
point, while Bit 15 corresponds to the highest numbered I/O point.
(BAR0 + 0x0000 002C –
0x0000 0034)
The Event Type Configuration Registers determine the type of input channel
transition that will generate an event for each of the forty-eight possible
event sensing channels. A “0” bit selects event on level transition. An event
will be generated when the input channel level specified by the Event
Polarity Register occurs (i.e. low or high-level transition event). A “1” bit
means the event will occur when a Change-Of-State (COS) occurs at the
corresponding input channel (i.e. any state transition, low to high or high to
low). Bit 0 of each register corresponds to the lowest numbered I/O point,
while Bit 15 corresponds to the highest numbered I/O point.
Note that no events will be detected until enabled via the Event Enable
Register. Further, interrupts will not be reported to the system unless the
Interrupt enable bit-0 has been configured for enable via the Interrupt
Register. All bits are set to “0” following a reset which means that, if
enabled, the inputs will cause events and/or interrupts for the levels
specified by the Interrupt Polarity Register.
