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Acqiris U5303A, User Manual

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4.2   Custom firmware capability (FPGA Development Kit)

U5303A User's Manual

59

4.2 Custom firmware capability (FPGA
Development Kit)

The -FDK (FPGA Development Kit) option allows the access to the on-board processing FPGA for
custom algorithm implementation.

For details, please contact technical support

[email protected]

.

Summary of Contents for U5303A

Page 1: ...Acqiris U5303A Acquisition Card 2 channels 12 bit 500 MS s to 4 GS s DC up to 2 GHz bandwidth with real timeprocessing User s Manual...

Page 2: ...greement and written consent from Acqiris SA as governed by international copyright laws Version July 2019 Contact us Acqiris Americas contact americas acqiris com Acqiris Europe contact emea acqiris...

Page 3: ...nnel input specifications 9 1 3 Sampling and Data Acquisition 11 1 4 Trigger 12 1 5 Calibration 14 Real Time Processing Options 16 2 1 Acquisition modes and specific features 16 2 2 Easy firmware swit...

Page 4: ...88 8 8 How to set the external trigger 89 8 9 How to perform binary decimation depending on firmware 90 8 10 How to perform partial readout 91 8 11 How to load a new firmware 94 8 12 How to switch fr...

Page 5: ...1 6 GS s or 2 GS s per channel depending on the option and up to 4 GS s in interleaved mode along with an analog bandwidth of up to 2 GHz and DDR3 acquisition memory options up to 4 GB The U5303A incl...

Page 6: ...Manual Block diagram Figure 1 1 U5303A block diagram Most of the technical specifications concerning your particular ADC card are covered in this manual however for the complete specifications please...

Page 7: ...Card Features U5303A User s Manual 7 Chapter 1 Main ADC Card Features 1 1 U5303A front panel features 8 1 2 Channel input specifications 9 1 3 Sampling and Data Acquisition 11 1 4 Trigger 12 1 5 Calib...

Page 8: ...UT MMCXfemale Trigger Outsignal User selectablefromseveralfunctions I O 1 2 3 MMCXfemale User configurableInput Outputsignal 3 3VCMOSand TTLcompatible CLK IN MMCXfemale Externalclockinput AC coupledan...

Page 9: ...SR3 Channel input The U5303A has the following front end capabilities Coupling Impedance Full Scale Ranges FSR Recommended maximum operating voltage Clamp level Absolute maximum DC voltage rating Off...

Page 10: ...er page 88 Options Input Frequency Range BW Limiter selection 1 V FSR 2 V FSR F05 SR0 DC to400MHz typical NoBWlimiter INT SR1 SR2 SR3 DC to650MHz typical 650MHz INT F10 SR1 SR2 SR3 DC to1 9GHz typical...

Page 11: ...ling Rate Available Channels Resolution Readout Modes U5303A SR0 0 5GS s 2 12bits Singleor multi record upto131 072records or continuous dependsonfirmware options SR0and INT 1GS s 1 SR1 1GS s 2 SR1and...

Page 12: ...ls with high frequency components this means that the signal acquired and displayed doesn t correspond exactly to the signal seen from the trigger comparator input Since the signal seen on the trigger...

Page 13: ...e rate 1 32 of the highest sample rate with interleaving If comparing the initial trigger time T0 measured using the same waveform either used as channel input trigger or as an external trigger the T0...

Page 14: ...uming because of the many possible configuration states Therefore the self calibration is performed only for the current configuration state and is mandatory before making the first acquisition with g...

Page 15: ...e corresponding to all datasheet specifications for every installed option If needed the DUT is adjusted and re qualified ensuring it is in line with full specifications Our ADC cards are calibrated a...

Page 16: ...ware options ordered with your products To check which options and mode are present on your ADC card you can use the MD3 Software Front Panel from the Windows Start Menu Acqiris MD3 Acqiris MD3 SFP Th...

Page 17: ...recorded with a single trigger The user selects the sampling rate and record size and sets the number of records to 1 default value For details about the trigger sources see Trigger page 12 Figure 2...

Page 18: ...om 1 point to the full amount of acquisition memory available Model Memory option ordered Acquisition memory Max samples channel U5303A M02 256MB 64MS ch M10 1GB 256MS ch M40 4GB 1GS ch Table 2 2 Maxi...

Page 19: ...th in digitizer mode depending on the record size post trigger delay and binary decimation factor Above this limit the driver returns a post trigger overflow This limitation is given by the table belo...

Page 20: ...steps of 8 triggers excepted when using less than 8 triggers Some possible values are 1 2 3 4 5 6 7 8 16 24 32 triggers Effective acquisition length from 1 up to 480 KSamples in interleaving mode or...

Page 21: ...oise base can be subtracted from each data value above threshold before the accumulation is done See Figure below The noise base should always be equal or smaller than the threshold Figure 2 4 Signal...

Page 22: ...ise Acqiris s ADC cards use several interleaved ADC cores In applications where multiple waveforms are accumulated the synchronicity between ADCs sequence and trigger results in a synchronous noise wh...

Page 23: ...m triggers the acquisition card Out AveragerAwg ControlIOs interface Self Trigger signal is propagated through the IO 3 Post trigger delay The post trigger delay is a multiple of 10 ns with SR2 option...

Page 24: ...s the baseline correction computation is active all the time b Between acquisitions the baseline calculation is active only outside the acquisition window i e from the trigger to the end of the record...

Page 25: ...averaging at that moment no need for a new start Out AccumulationActive ADC card output IO 2 This signal informs that the ADC card is busy accumulating Out AcquisitionActive ADC card output IO 1 or IO...

Page 26: ...If the number of acquired triggers is between 16 and 24 the data accumulation for the first 16 triggers can be read And so on in multiple of 8 accumulations After an Acquisition Abort and an incomplet...

Page 27: ...vailable For IVI C C1 Program Files IVI Foundation IVI Drivers AqMD3 Examples IVI C For IVI NET C Program Files IVI Foundation IVI Drivers AqMD3 Examples IVI NET AVG Configuration The interfaces metho...

Page 28: ...the self trigger mode to Cus tom Wave AqMD3_NSAConfigure Configures the Noise Suppressed Accumulation prop erties AqMD3_FetchAc cumulatedWaveformInt32 This function returns the accumulated waveform w...

Page 29: ...tion AQMD3_ATTR_NSA_ ENABLED Specifies whether the Noise Suppressed Accumulation is active This attribute affects card behavior only when the Acquisition Mode attribute is set to Averager AQMD3_ATTR_N...

Page 30: ...2 4 Real time averaging AVG option 30 U5303A User s Manual IVI NET...

Page 31: ...ope Specifies whetherarisingorafallingedgeof thegeneratedwaveform triggers theADC card IAqMD3TriggerSourceSelfTrigger CustomWave LoadConfigurationFile Loads theconfigurationfortheself trigger generato...

Page 32: ...edforthespe cifiedchannel This waveform is from apre viously initiatedaccumulatedacquisitionin AveragerorPeak Detectionmode Returned waveform dataunits areVolts Interface Method Property name Descript...

Page 33: ...ronous noise Baseline stabilization algorithm and digital offset Peak detection algorithm Nine samples are used to validate if a sample corresponds to a peak the sample itself along with the four samp...

Page 34: ...in PKD mode Current solution supports a single sequence mode The number of potential trigger lost depends on several factors The time needed to perform the last accumulation PKDDead Time which depend...

Page 35: ...configured to define the baseline margins and avoid non desired signal data in the computation as illustrated below In addition a digital offset can be applied after the baseline stabilization Figure...

Page 36: ...and outputs IO 1 2 in the front panel may be used to control the accumulation or read the ADC card status Parameters ControlIO interface In AccumulationEnable ADC card input IO 1 This signal controls...

Page 37: ...Examples IVI NET IVI C Functions AqMD3_SelfTriggerAbortGeneration AqMD3_SelfTriggerInitiateGeneration AqMD3_SelfTriggerSquareWaveConfigure AqMD3_SelfTriggerCustomWaveLoadConfigurationFile AqMD3_Basel...

Page 38: ...requency IAqMD3TriggerSourceSelfTriggerSquareWave Slope IAqMD3TriggerSourceSelfTriggerCustomWave LoadConfigurationFile IAqMD3Acquisition Mode IAqMD3Acquisition NumberOfAverages IAqMD3Channel DataInver...

Page 39: ...nd readout modes are Single record mode one shot with single waveform with a single trigger Multi record mode one shot with multiple waveforms with multiple triggers Figure 3 1 Acquisition sequence us...

Page 40: ...o readout multiple streams while the acquisition is still running CSR is only available with the standard digitizer mode DGT Standard acquisition vs CSR acquisition With the standard acquisition and r...

Page 41: ...ts etc A data stream is characterized by the following parameters Data Rate Amount of data generated per second Available Buffer Size Amount of internal buffer memory available Data Organization How d...

Page 42: ...cation by several mechanisms Down sampling or decimation allows to reduce the acquisition sample rate by performing a bin ary decimation possible decimation factors are 2 4 and 8 Truncation 8 bit 10 b...

Page 43: ...ing rate and the data format U5303A SR1 1 GS s SR2 1 6 GS s defaultmode 12 bitraw on16 bit 2GB s 3 2GB s 12 bitmode 1 5GB s 2 4GB s 10 bitmode 1 25GB s 2GB s 8 bitmode 1GB s 1 6GB s Emulation mode Wit...

Page 44: ...32 will successfully fetch the remaining data available in the internal buffer and will throw an overflow exception once the internal buffer is empty If any stream reaches the internal data buffer ful...

Page 45: ...cquisition and Readout CSR U5303A User s Manual 45 Figure 3 6 CSR acquisition sequence To optimize the application data throughput it is recommended to use NbOfElementsToFetch 1 M especially for appli...

Page 46: ...aA for long i long FirstValidElementsA i long FirstValidElementsA ActualElementsA i _int16 s1 pDataA i 0xFFFF _int16 s2 pDataA i 16 0xFFFF printf d n d n s1 s2 SafeArrayUnaccessData psaWfmDataA CSR Co...

Page 47: ...ITS_PER_ MARKER Numberof bits representingaMarkervalue AQMD3_ATTR_STREAM_MARKERS_FRACTIONAL_ BITS Numberof fractional bits intheMarkervalue AQMD3_ATTR_STREAM_MINMAX_FRAME_SIZE Numberof samples overwhi...

Page 48: ...of datafortheFetchDataoperations MaxSizeInBytes Indicates themaximal sizeof datafortheFetchDataoperations IAqMD3StreamMarkers BitsPerMarker Numberof bits representingaMarkervalue FractionalBits Number...

Page 49: ...Functional description Standard acquisition and readout vs TSR mode In a standard multi record acquisition and readout the duration of the acquisition is limited by the ADC card internal buffer memory...

Page 50: ...a and store them into a circular buffer which can be read simultaneously Once the Acquisition is initiated the user has to poll on the TSR IsAcquisitionComplete property to check for the availability...

Page 51: ...Files IVI Foundation IVI Drivers AqMD3 Examples IVI C For IVI NET C Program Files IVI Foundation IVI Drivers AqMD3 Examples IVI NET Due to design constraints the number of trigger events needed to ha...

Page 52: ...SR 52 U5303A User s Manual AQMD3_ATTR_TSR_MEMORY_OVERFLOW_OCCURRED IVI NET Interface Method Property name IAqMD3AcquisitionTSR Continue IAqMD3AcquisitionTSR Enabled IAqMD3AcquisitionTSR IsAcquisitionC...

Page 53: ...veraging AVG option page 20 The addition of simultaneous acquisition and readout feature TSR on top of real time averaging enable minimal dead time between accumulations Functional description The arc...

Page 54: ...he number of averages for an averager sequence can be selected from 1 to 520 000 triggers Abort function is not yet supported in AVG TSR mode The workaround is to close and reinitialize the card Usage...

Page 55: ...3 4 Averager with triggered simultaneous acquisition and readout AVG TSR INT option U5303A User s Manual 55 Figure 3 10 AVG TSR acquisition sequence...

Page 56: ...risk of overflow only with configurations using minimum number of averages and very high trigger rate If an overflow occurs the writing is disabled implying that follow on triggers may be lost A prop...

Page 57: ...board signal processing features that can be enable e g to optimize signal performance or reduce data volume depending on each application These features are common to the acquisition modes excepted w...

Page 58: ...e to required decimated sampling rate Sampling rate option Acquisition mode Maximum Decimation Ratio Lower supported sampling rate SR0 Notsupported NA SR1 Singlerecord 210 976 56kS s Multi Record 25 3...

Page 59: ...A User s Manual 59 4 2 Custom firmware capability FPGA Development Kit The FDK FPGA Development Kit option allows the access to the on board processing FPGA for custom algorithm implementation For det...

Page 60: ...te SR0 400 MHz bandwidth F05 256 MB acquisition memory M02 LX195T DPU FPGA The SS2 and SS3 options are using a U5303A pre configured version composed of 1 GS s sampling rate SR1 650 MHz bandwidth F05...

Page 61: ...Synchronization U5303A User s Manual 61 Chapter 6 Control and Synchronization 6 1 External clock and reference 62 6 2 Trigger modes and time stamps 63 6 3 Trigger output 67 6 4 Multi purpose inputs an...

Page 62: ...MS s 900MS sto1GS s 900MS sto1 6GS s 1 5GS sto2GS s Resultingsamplingrate withinterleaving INT option NA 1 8GS sto2GS s NA MinimumAmplitude 0 5Vppinto50 MaximumPower 15dBm MaximumVoltage 10V Threshold...

Page 63: ...al should be applied to all of them 6 2 Trigger modes and time stamps Trigger modes As listed previously the trigger source can be the signal applied to an input channel internal triggering an externa...

Page 64: ...e end of the acquired waveform The condition of 0 pre trigger which is identical to a post trigger of 0 indicates that all data points are acquired immediately after the trigger i e the trigger point...

Page 65: ...reset each time the time reference is configured Parameters IVI C InitialXTimeSeconds Specifies the seconds portion of the absolute time at which the first data point was acquired InitialXTimeFractio...

Page 66: ...e absolute time at which this measurement was triggered Note that this differs from Start Time in that the trigger may have occurred at some time other than when the first data point was captured as i...

Page 67: ...SeeSelftrigger mode page22 HighLevel Fixedhighlevelsignalfor debugpurposes LowLevel default Fixedlow levelsignalfor debugpurposes Table 6 3 List of supported trigger out signals Trigger output signal...

Page 68: ...l HighLevel TriggerAccepted TriggerAcceptedResync TriggerCompare IVI NET IAqMD3TriggerOutput Source IAqMD3TriggerOutput Enabled Boolean IAqMD3TriggerOutput Offset Double Specifications Figure 6 2 Trig...

Page 69: ...utput U5303A User s Manual 69 Figure 6 3 Suggested trigger signal terminations The external trigger output functionality is implemented in the hardware No trigger out signal occurs for software genera...

Page 70: ...deterministic clockcyclelatency FDK Out FPGASyncOut Pulse TheSyncOutoutputsignalfromtheDPU user core ThissignalistransferredfromtheDPU to theControlFPGAwithadeterministicclock cyclelatency FDK Out 10...

Page 71: ...V 2 0to3 45V Output Intherange0to0 8V Intherange1 6to3 3V Table 6 5 Logic levels As an Input The input is high impedance and will be pulled high if unconnected via an internal weak pull up 42 2 k pull...

Page 72: ...wing development environments Visual C Visual C CLI Visual Basic NET Driver API documentation The AqMD3 APIdocumentation can also be accessed from IVI C Start Acqiris MD3 Documentation AqMD3 C IVI Dri...

Page 73: ...lib must be referenced This section demonstrates usage of the driver using instrument specific references All IVI C driver programs must do the following include AqMD3 h Link to AqMD3 lib Prefix func...

Page 74: ...VI_FALSE Setup IVI defined initialization options ViConstString standardInitOptions Cache true InterchangeCheck false QueryInstrStatus true RangeCheck true RecordCoercions false Simulate false status...

Page 75: ...MD2 2 x to MD3 3 x Please refer to the following documents for guidelines accessible from Start Acqiris MD3 Documentation or from C Program Files Acqiris MD3 Documentation AgMD2 to AqMD3 IVI C Softwa...

Page 76: ...ernal1 Trigger delay 0 ns Trigger type Edge Trigger coupling DC Trigger level 0 Volts Trigger slope Positive Interleave Disable Mode Normal DGT Samplingrate DependsonSRxoption Defaultisthehigher value...

Page 77: ...erform an implicit ApplySetup before the actual action Actions with implicit ApplySetup Method name Description SelfTest Toinsurethecardisactuallyinthedesiredstatebeforedoingtheselftest SelfCalibrate...

Page 78: ...How to generate a software trigger 86 8 6 How to perform time interleaving acquisitions 87 8 7 How to enable or bypass the bandwidth limiter 88 8 8 How to set the external trigger 89 8 9 How to perfo...

Page 79: ...ses include stdio h include visa h int main ViSession rm VI_NULL viOpenDefaultRM rm ViChar search PXI INSTR ViFindList find VI_NULL ViUInt32 count 0 ViChar rsrc 256 ViStatus status viFindRsrc rm searc...

Page 80: ...libration implemented in MD3 drivers allows to save time by automatically keeping in memory the calibration information from any self calibration performed since the beginning of the session When the...

Page 81: ...kmode Externalclockfrequency Eachtimethisparameter changes Clocksource Eachtimethisparameter changes The channel parameters are calibrated independently per channel Saving and restoring calibration se...

Page 82: ...ock external reference oscillator 3 Call SelfCalibrate once for each trigger source user intends to use 4 Call Calibration LoadFromFile to restore the previously saved calibration state 5 The calibrat...

Page 83: ...8 2 How to calibrate the card U5303A User s Manual 83 IVI NET Interface Method Property name IAqMD3Calibration IsRequired SelfCalibrate SaveToFile LoadFromFile...

Page 84: ...nce Fetch acquired data Giving a null pointer as data array to the fetch function means the driver will allocate the proper amount of memory during the fetch call Ivi Digitizer IWaveformCollection Int...

Page 85: ...FDKoptiononly DPUA DDR3A DPUA DDR3B MonitoringValue Theseparametersarefor informationonlyor canbeusedfor debuggingpurpose ThereareaccessiblethroughtheMD3SFPor thecommandbelow Pleaserefer to AqMD3 chm...

Page 86: ...reTrigger IVI C or to method IAqMD3Trigger SendSoftwareTrigger IVI NET sends a single software trigger SendSoftwareTrigger must be called as many times as required Multi record acquisitions required a...

Page 87: ...IVI C AqMD3_SetAttributeViString session Channel1 AQMD3_ATTR_TIME_INTERLEAVED_CHANNEL_LIST Channel2 AqMD3_SetAttributeViReal64 session AQMD3_ATTR_SAMPLE_RATE 3 2e9 Channels time interleaving IVI NET...

Page 88: ...nable the filter Using the AqMD3 IVI C driver AqMD3_SetAttributeViBoolean session Channel1 AQMD3_ATTR_INPUT_FILTER_BYPASS VI_FALSE Using the AqMD3 IVI NET driver driver Channels L Channel1 Filter Bypa...

Page 89: ...AqMD3_SetAttributeViString session AQMD3_ATTR_ACTIVE_TRIGGER_SOURCE External1 AqMD3_SetAttributeViReal64 session External1 AQMD3_ATTR_TRIGGER_LEVEL level IVI NET spDriver Trigger ActiveSource Externa...

Page 90: ...factors depend on the channel configuration CHx and sampling rate SRx options of your digitizer Please refer to Sampling and Data Acquisition page 11 section for more information Using the AqMD3 IVI...

Page 91: ...is possible to read the data partially using several calls to AqMD3_ FetchMultiRecordWaveformXXX IVI C or MultiRecordMeasurement FetchMultiRecordWaveform IVI NET function defining the first record th...

Page 92: ...Size if status VI_SUCCESS handle errors and warnings Allocate memory for waveform data dataArray ViInt16 malloc size_t arraySize sizeof ViInt16 Fetch the first numPointToRead data status AqMD3_FetchMu...

Page 93: ...umber of records and points to fetch var waveforms driver Acquisition CreateWaveformCollectionInt32 numRecordsToRead numPointToRead To first the first numPointToRead data waveforms driver Channels cha...

Page 94: ...ser s Manual 8 11 How to load a new firmware The on board FPGAs field programmable gate arrays contain processor logic needed to efficiently execute several crucial functions They will be automaticall...

Page 95: ...not supported for Acquisition Mode Averager or PeakDetection IDispatch error 28176 The averager mode or peak detection mode is supported with a single record only When you want to change the acquisiti...

Page 96: ...gnal with reference signal expected values This utility checks the version of control FPGA firmware already loaded If necessary it pro poses to update the firmware using the Firmware Update Utility Yo...

Page 97: ...D3Verify U5303A User s Manual 97 When the version of control FPGA firmware is updated and successful please power off your computer restart it again for the update to take effect and process AqMD3Veri...

Page 98: ...high voltage surge of up to 5 kV The overvoltage protection kit contains 2 parts A 3dB SMA Attenuator Length 22 mm Diameter 7 1 mm Weight 4 g A 90 V SMA Spark Gap Length 39 5 mm Diameter 15 3 mm Weig...

Page 99: ...1 PCIe module with Input Over voltage protection fitted Figure 10 2 Both the Spark Gap and the Attenuator MUST be used together in order to fully protect the modules In order to limit the input curren...

Page 100: ...if we have Nsamples 211 and Fs 100e6 and we expect and input frequency close to Fs 2 let s say Fin 44 MHz then Ncycles 901 12 which is close to an integer We could therefore round down to Ncycles 901...

Page 101: ...nditions This parameter is provided for information only 11 3 Q What are the differences between the various data streaming firmware options supported by high speed ADC cards A Acqiris ADC cards offer...

Page 102: ...transfer performance is higher with CST or CSR and data transfer performance independent of trigger settings record size 11 4 Q What happens if the host processor goes in hibernation mode A Hibernatio...

Page 103: ...products Only properly trained service personnel may perform installation and service procedures Operator is responsible to maintain safe operating conditions To ensure safe operating conditions card...

Page 104: ...power from the entire test system and discharge any capacitors before connecting or disconnecting cables or jumpers installing or removing ADC cards or making internal changes such as installing or r...

Page 105: ...the European Community Australian Communication and Media Authority mark to indicate regulatory compliance as a registered supplier This symbol indicates product compliance with the Canadian Interfere...

Page 106: ...scharge ESD ESD can damage the highly sensitive components in your card ESD damage is most likely to occur as the module is being installed or when cables are connected or disconnected Protect the cir...

Page 107: ...y standard PCI Express format benefit from the very high data transfer rates of the PCIe interface and occupying a single slot in a host PC They also feature programmable on board processing capabilit...

Page 108: ...This information is subject to change without notice Acqiris SA 2017 2019 Wednesday July 10 2019 Switzerland www acqiris com...

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